An FPGA Implementation of GCN with Sparse Adjacency Matrix

Ding, Luchang; Huang, Zhize; Chen, Gengsheng

doi:10.1109/asicon47005.2019.8983647

Cited by 10 publications

(3 citation statements)

References 3 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…AWB-GCN [11] implements amount of process elements for multiply-accumulate-cell (MAC) and balance the workload of process elements to accelerate the sparse matrix multiplication. Other works [10,13,14] accelerate GCNs by designing efficient pipeline architecture, optimizing memory mode, and increasing parallelism.…”

Section: B Deep Learning Inference Acceleratorsmentioning

confidence: 99%

“…In contrast, there are two memory synchronizations between the three steps of each layer in GATs because of the masked self-attention mechanism [1]. The basic calculation of the existing works on GCNs and CNNs [10][11][12][13][14][15][16][17][18][19] has no change which still use multiplication with heavy dependence on DSPs. Moreover, the loss of accuracy is not detailed studied.…”

Section: B Deep Learning Inference Acceleratorsmentioning

confidence: 99%

“…To reduce the cost, several efforts have been devoted to develop accelerators. But these works most focus on parallelizing computation to accelerate Convolutional Neural Networks (CNNs) [15][16][17][18][19][32][33][34], GCNs [11][12][13][14] or graph analysis [20][21][22][23] on Field Programmable Gate Array (FPGA), Graphics Processing Unit (GPU) or multi-core platform [30]. How to accelerate inference of GATs by exploiting the FPGA hardware still remains an open issue.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

FPGAN: An FPGA Accelerator for Graph Attention Networks With Software and Hardware Co-Optimization

2020

View full text Add to dashboard Cite

The Graph Attention Networks (GATs) exhibit outstanding performance in multiple authoritative node classification benchmark tests (including transductive and inductive). The purpose of this research is to implement an FPGA-based accelerator called FPGAN for graph attention networks that achieves significant improvement on performance and energy efficiency without losing accuracy compared with PyTorch baseline. It eliminates the dependence on digital signal processors (DSPs) and large amounts of on-chip memory and can even work well on low-end FPGA devices. We design FPGAN with software and hardware co-optimization across the full stack from algorithm through architecture. Specifically, we compress model to reduce the model size, quantify features to perform fixed-point calculation, replace multiplication addition cell (MAC) with shift addition units (SAUs) to eliminate the dependence on DSPs, and design an efficient algorithm to approximate SoftMax function. We also adjust the activation functions and fuse operations to further reduce the computation requirement. Moreover, all data is vectorized and aligned for scalable vector computation and efficient memory access. All the above optimizations are integrated into a universal hardware pipeline for various structures of GATs. We evaluate our design on an Inspur F10A board with an Intel Arria 10 GX1150 and 16 GB DDR3 memory. Experimental results show that FPGAN can achieve 7.34 times speedup over Nvidia Tesla V100 and 593 times over Xeon CPU Gold 5115 while maintaining accuracy, and 48 times and 2400 times on energy efficiency respectively.

show abstract

Section: B Deep Learning Inference Acceleratorsmentioning

confidence: 99%