An FPGA implementation of low-latency video transmission system using lossless and near-lossless line-based compression

Inatsuki, Takahiro; Morinaga, Kosuke; Tsutsui, Hiroshi; Miyanaga, Yoshikazu

doi:10.1109/icdsp.2015.7252041

Cited by 11 publications

(3 citation statements)

References 9 publications

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“…Inatsuki et al [35] presented the FPGA implementation of low-latency video transmission system by using the line-based compression technique. They proposed the scalable architecture to provide the bit truncation that ultimately reduced the data rate.…”

Section: Related Workmentioning

confidence: 99%

FPGA-based Auxiliary Minutest MQ-coder architecture of JPEG2000

Jayavathi¹,

Shenbagavalli²

2017

J Real-Time Image Proc

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Embedded Block Coding with Optimized Truncation (EBCOT) used in JPEG2000 standard performs the sequential processing of code blocks for clear images. The employment of Matrix Quantizer (MQ) in EBCOT reduces the computational burden by generating the context decision pair from probabilistic estimation. But, it consumes huge devices and occupies large memory space that leads to the difficulties in hardware design. The bit truncation in MQ-coder reduces the computational complexities that lead to a reduction in the memory space occupation in the hardware platform. This paper proposes the Auxiliary Minutest MQ (AMMQ) architecture for bit truncation in the probability estimation of context decision pair making. The reduction in a number of bits minimizes the slice registers and lookup tables utilization that offers less flipflop consumption to achieve the compact chip development for JPEG2000 compression. Besides, the reduction in computational steps effectively minimizes the time delay and hence the high operating frequency. The comparative analysis of proposed AMMQ-coder architecture with the existing architectures regarding the memory assures the effectiveness of new way of bit truncation scheme in the JPEG2000 compression.

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Section: Related Workmentioning

confidence: 99%

FPGA-based Auxiliary Minutest MQ-coder architecture of JPEG2000

Jayavathi¹,

Shenbagavalli²

2017

J Real-Time Image Proc

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“…DOI: https://doi.org/10.33103/uot.ijccce.21. 1.6 In 2015, T. Inatsuki et al [10] the authors suggested real-time lossless and near-lossless video compression and implement it by using JPEG-Ls and DPCM algorithm and using Huffman coding as an entropy encoder; and this system achieves a compression ratio of 1.818, and the maximum data throughput is 148.5 Mpixles/s.…”

Section: Introductionmentioning

confidence: 99%

“…In 2017, A. H. Hussein et al [12], the authors offered modified run-length encoding to compressed an image. The authors suggested a technique to improve the compression ratio, as they assumed that if the difference between adjacent pixels was less than (10), meaning that if the current pixel is equal to or greater by ten or smaller by ten than the previous pixel, the two pixels are considered identical. They have applied this method to a group of pictures, and the compression ratio ranged between (5.48-1.07).…”

Section: Introductionmentioning

confidence: 99%

Video Compression Based on FPGA Using SIMD Architecture

Shnain¹,

Abdullah²,

Jeiad³

2021

IJCCCE

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Recently, video files and images have became the dominant media material for transmitting or storing across different applications that are used by different people. So, there was a serious need to find more effective and efficient video compression techniques to reduce the large size of such multimedia files. This paper proposes SIMD based FPGA lossless JPEG video compression system with the facility of scalability. Generally, the proposed system consists of a software side and a hardware side. The digital video file is prepared to be processed by the hardware side frame by frame on the software side. The hardware side is proposed to consist of two main processing circuits, which are the prediction circuit for calculating the predicted value of each pixel in the certain frame and the encoding circuit that was represented by a modified RLE (Run-Length-Encoder) to encode the result obtained through subtracting the predicted value from the real value for each pixel to produce the final compressed video file. The compression ratio obtained for the proposed system is equal to 1.7493. The throughput improvement for the two and four processing units basing on SIMD architecture was 100 MP/s and 200 MP/s, respectively. The clock results showed that the number of clocks required had become 50% and 25% when using two processing units and four processing units, respectively, from the number of clocks using single processing units. Index Terms— Video Compression, Lossless JPEG, RLE, FPGA.

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Image and Video Coding

2023

Design for Embedded Image Processing on FPGAs

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An FPGA implementation of low-latency video transmission system using lossless and near-lossless line-based compression

Cited by 11 publications

References 9 publications

FPGA-based Auxiliary Minutest MQ-coder architecture of JPEG2000

FPGA-based Auxiliary Minutest MQ-coder architecture of JPEG2000

Video Compression Based on FPGA Using SIMD Architecture

Image and Video Coding

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