2018
DOI: 10.1016/j.compeleceng.2017.06.009
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An FPGA implementation of novel smart antenna algorithm in tracking systems for smart cities

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Cited by 9 publications
(4 citation statements)
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References 14 publications
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“…Also, its execution time is comparable to the others. (Dikmese et al 2010(Dikmese et al , 2011 Xilinx virtex 4 (XC4VLX60, 500 MHz) 0.022 LMS (Dikmese et al 2010(Dikmese et al , 2011 Xilinx virtex 4 (XC4VLX60, 500 MHz) 0.059 CM (Dikmese et al 2010(Dikmese et al , 2011 Xilinx virtex 4 (XC4VLX60, 500 MHz) 0.091 MSR-CORDIC (Thiripurasundari et al 2017) Xilinx virtex 4 (XC4VLX60, 500 MHz) 0.017 QRD-RLS (Dick et al 2006) Xilinx virtex 4 (XC4VLX60, 250 MHz) 0.057 D 3 (Jarrah and Jamali 2013) Xilinx Artix 7 (XA7A100T, 8.45 MHz) 6…”
Section: Resultsmentioning
confidence: 99%
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“…Also, its execution time is comparable to the others. (Dikmese et al 2010(Dikmese et al , 2011 Xilinx virtex 4 (XC4VLX60, 500 MHz) 0.022 LMS (Dikmese et al 2010(Dikmese et al , 2011 Xilinx virtex 4 (XC4VLX60, 500 MHz) 0.059 CM (Dikmese et al 2010(Dikmese et al , 2011 Xilinx virtex 4 (XC4VLX60, 500 MHz) 0.091 MSR-CORDIC (Thiripurasundari et al 2017) Xilinx virtex 4 (XC4VLX60, 500 MHz) 0.017 QRD-RLS (Dick et al 2006) Xilinx virtex 4 (XC4VLX60, 250 MHz) 0.057 D 3 (Jarrah and Jamali 2013) Xilinx Artix 7 (XA7A100T, 8.45 MHz) 6…”
Section: Resultsmentioning
confidence: 99%
“…As a beamforming algorithm, Thiripurasundari et al 2017 proposed a modified CORDIC based on the QR Decomposition-Recursive Least-Squares (QRD-RLS) method named Mixed Scaling Rotation COordinate Rotation DIgital Computer (MSR-CORDIC). It is developed using the Verilog Hardware Description Language (HDL) and implemented on the Xilinx FPGA board.…”
Section: Related Workmentioning
confidence: 99%
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“…In [13], beamforming and direction of arrival (DOA) using the MSR-CORDIC and MUSIC algorithms, respectively. The proposed algorithm is developed using Verilog HDL and implemented using the Xilinx field-programmable gate array (FPGA).…”
Section: Introductionmentioning
confidence: 99%