An FPGA Implementation of UAV SAR Real-time Imaging Algorithm

Joint UAV deployment, SF placement, and collaborative task scheduling in heterogeneous multi‐UAV‐empowered edge intelligence

“…Therefore, Constraints (4), (7), and ( 10) are all satisfied. Finally, based on the matrix V , A, and O, the maximum overall revenue G max and the suboptimal solution of SF placement and collaborative task scheduling X can be obtained (in steps [5][6][7][8][9][10][11][12][13][14][15]. The initialization of V = (v i j ) K ×K and O = (o i j ) K ×K is shown in Algorithm 2.…”

“…The AI CPs, such as Field Programmable Gate Array (FPGA), GPU, and Application Specific Integrated Circuit (ASIC), handle the AI workload and leave the rest of the task to the CPU [6,7]. FPGA has been treated as a promising solution to supplant conventional processors for performing computation-intensive tasks [8][9][10][11], such as deep neural network (DNN)-based image recognition, on the UAV platforms without violating size, weight, and power constraints inherent to UAV design [12][13][14][15]. Unless otherwise stated, we adopt FPGAs as the CPs in the following analysis.…”