An FPGA-in-the-loop approach for HDL motor controller verification

Rogers, Paul; Kavasseri, Rajesh G.; Smith, Scott C.

doi:10.1109/reconfig.2017.8279774

Cited by 5 publications

(4 citation statements)

References 14 publications

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“…Such EDA environments enable software engineers to design system-level/chip-level solutions, and ultimately to design optimized and effective hardware implementations. This approach also enables the effective holistic modelling and functional simulation of complex systems based on SoC electronic controllers, with a plethora of applications such as: mechatronics [64,65], robotics [66,67], automation [68], security [69], power electronics [70], energy systems [71], electric drives [72], and IoT systems [73][74][75][76][77].…”

Section: Brief Comparative Analysis Of Soc Design Methodologies and T...mentioning

confidence: 99%

Digital Electronic System-on-Chip Design: Methodologies, Tools, Evolution, and Trends

Cirstea,

Benkrid,

Dinu

et al. 2024

Micromachines

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This paper reviews the evolution of methodologies and tools for modeling, simulation, and design of digital electronic system-on-chip (SoC) implementations, with a focus on industrial electronics applications. Key technological, economic, and geopolitical trends are presented at the outset, before reviewing SoC design methodologies and tools. The fundamentals of SoC design flows are laid out. The paper then exposes the crucial role of the intellectual property (IP) industry in the relentless improvements in performance, power, area, and cost (PPAC) attributes of SoCs. High abstraction levels in design capture and increasingly automated design tools (e.g., for verification and validation, synthesis, place, and route) continue to push the boundaries. Aerospace and automotive domains are included as brief case studies. This paper also presents current and future trends in SoC design and implementation including the rising, evolution, and usage of machine learning (ML) and artificial intelligence (AI) algorithms, techniques, and tools, which promise even greater PPAC optimizations.

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Section: Brief Comparative Analysis Of Soc Design Methodologies and T...mentioning

confidence: 99%

Digital Electronic System-on-Chip Design: Methodologies, Tools, Evolution, and Trends

Cirstea,

Benkrid,

Dinu

et al. 2024

Micromachines

View full text Add to dashboard Cite

show abstract

“…At this point, the sum of the action time of adjacent voltage vectors was greater than the switching period, that is, T 4 + T 6 > T s . The action time of the actual voltage vector reduced proportionally, as expressed in Equations ( 18) and (19). In the linear modulation region, the reference voltage vector amplitude range was 0 ≤ Vref ≤ /√3.…”

Section: Methods 4: Svpwm Overmodulation Design Methodsmentioning

confidence: 99%

“…When the reference voltage vector trajectory was in the DEG region, the actual voltage vector was consistent with the base voltage vector OE (V 6 ). When the trajectory of the reference voltage vector was located in the region composed of arc BE and straight lines BG and EG, the action time of the actual voltage vector would be reduced proportionally, and the reduction method was the same as the calculation method of Equations ( 18) and (19). When the amplitude of the reference voltage vector reached 2U dc / √ 3, the trajectory of the actual output voltage vector jumped between the six vertices of the regular hexagon, i.e., from OB to OE, with a dwell time of 1/6 period at each vertex.…”

Section: Startmentioning

confidence: 99%

“…In recent years, certain vector control algorithms have been applied to FPGA to realize its acceleration [11][12][13][14][15]. Loop operation of vector control through FPGA has also been applied [16][17][18][19][20], greatly improving the operation speed of the current loop. Besides, the PMSM vector control ASIC has been designed to improve the integration of the system [21].…”

Section: Introductionmentioning

confidence: 99%

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Design and Implementation of an Efficient Hardware Coprocessor IP Core for Multi-axis Servo Control Based on Universal SoC

et al. 2023

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The multi-axis servo control system has been extensively used in industrial control. However, the applications of traditional MCU and DSP chips in high-performance multi-axis servo control systems are becoming increasingly difficult due to their lack of computing power. Although FPGA chips can meet the computing power requirements of high-performance multi-axis servo control systems, their versatility is insufficient, and the chip is too costly for large-scale use. Therefore, when designing the universal SoC, it is better to directly embed the coprocessor IP core dedicated to accelerating the multi-motor vector control current loop operation into the universal SoC. In this study, a coprocessor IP core that can be flexibly embedded in a universal SoC was designed. The IP core based on time division multiplexing (TDM) technology could accelerate the multi-motor vector control current loop operation according to the hardware–software coordination scheme proposed in this study. The IP was first integrated into a universal SoC to verify its performance, and then the FPGA prototype verification for the SoC was performed under three-axis servo control systems. Secondly, the ASIC implementation of the IP was also conducted based on the CSMC 90 nm process library. The experimental results revealed that the IP had a small area and low power consumption and was suitable for application in universal SoC. Therefore, the cheap and low-power single universal SoC with the coprocessor IP can be suitable for multi-axis servo control.

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Design and Validation of a FPGA-Based HIL Simulator for Minimum Losses Control of a PMSM

Galioto

Sferlazza

Giaconia

2021

Lecture Notes in Electrical Engineering

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This work examines the FPGA programmable logic platforms applied to minimum losses control of a Permanent Magnet Synchronous Motor (PMSM), which represents a flexible solution for the implementation of an advanced digital control algorithm, given their intrinsic parallel structure and the capability to be directly reprogrammable in the field. In particular, design and validation of a FPGAbased Hardware-In-the-Loop (HIL) simulator is proposed, by investigating about data format, quantization and discretization effects and other issues arising during the experimental validation of a controller prototype, in order to reduce the embedded software development cycle and test control systems. The proposed simulator has been applied to control a PMSM. Specifically, two different minimum losses control techniques have been implemented as well as a space vector modulation of a three-phases voltage source inverter. The results given in this paper show the comparison of this two different algorithms and the effectiveness of the proposed HIL simulator.

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An FPGA-in-the-loop approach for HDL motor controller verification

Cited by 5 publications

References 14 publications

Digital Electronic System-on-Chip Design: Methodologies, Tools, Evolution, and Trends

Digital Electronic System-on-Chip Design: Methodologies, Tools, Evolution, and Trends

Design and Implementation of an Efficient Hardware Coprocessor IP Core for Multi-axis Servo Control Based on Universal SoC

Design and Validation of a FPGA-Based HIL Simulator for Minimum Losses Control of a PMSM

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