An FPGA Platform for Real-Time Simulation of Spiking Neuronal Networks

Pani, Danilo; Meloni, Paolo; Tuveri, Giuseppe; Palumbo, Francesca; Massobrio, Paolo; Raffo, Luigi

doi:10.3389/fnins.2017.00090

Cited by 70 publications

(35 citation statements)

References 44 publications

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“…While some works exploit either Hodgkin-Huxley neuron model or its variants (Zhang et al, 2013 ; Smaragdos et al, 2014 ; Osorio, 2016 ; Yang et al, 2017 ), some other works utilize its reduced forms (Graas et al, 2004 ; Yaghini Bonabi et al, 2014 ). Meanwhile, the majority of researchers use simple neuron models such as Izhikevich or leaky integrate and fire (Cassidy et al, 2007 ; Soleimani et al, 2012 ; Ambroise et al, 2013 ; Furber et al, 2013 ; Cheung et al, 2016 ; Pani et al, 2017 ) to cope with the computational complexity of the HH model.…”

Section: Discussionmentioning

confidence: 99%

“…A recent study proposes an FPGA implementation of 1440 Izhikevich neurons in a fully connected network (Pani et al, 2017 ). Although there are some similarities between their study and our proposed architecture such as scalability and modularity, a number of differences exist.…”

Section: Discussionmentioning

confidence: 99%

“…The final design is implemented on a Xilinx Virtex 7 FPGA. Another example is the work reported in Pani et al ( 2017 ). They utilize Xilinx Virtex 6 to implement a 1440 fully connected network using Izhikevic neuron model.…”

Section: Introductionmentioning

confidence: 89%

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A Scalable FPGA Architecture for Randomly Connected Networks of Hodgkin-Huxley Neurons

et al. 2018

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Human intelligence relies on the vast number of neurons and their interconnections that form a parallel computing engine. If we tend to design a brain-like machine, we will have no choice but to employ many spiking neurons, each one has a large number of synapses. Such a neuronal network is not only compute-intensive but also memory-intensive. The performance and the configurability of the modern FPGAs make them suitable hardware solutions to deal with these challenges. This paper presents a scalable architecture to simulate a randomly connected network of Hodgkin-Huxley neurons. To demonstrate that our architecture eliminates the need to use a high-end device, we employ the XC7A200T, a member of the mid-range Xilinx Artix®-7 family, as our target device. A set of techniques are proposed to reduce the memory usage and computational requirements. Here we introduce a multi-core architecture in which each core can update the states of a group of neurons stored in its corresponding memory bank. The proposed system uses a novel method to generate the connectivity vectors on the fly instead of storing them in a huge memory. This technique is based on a cyclic permutation of a single prestored connectivity vector per core. Moreover, to reduce both the resource usage and the computational latency even more, a novel approximate two-level counter is introduced to count the number of the spikes at the synapse for the sparse network. The first level is a low cost saturated counter implemented on FPGA lookup tables that reduces the number of inputs to the second level exact adder tree. It, therefore, results in much lower hardware cost for the counter circuit. These techniques along with pipelining make it possible to have a high-performance, scalable architecture, which could be configured for either a real-time simulation of up to 5120 neurons or a large-scale simulation of up to 65536 neurons in an appropriate execution time on a cost-optimized FPGA.

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Section: Discussionmentioning

confidence: 99%

Section: Discussionmentioning

confidence: 99%

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A Scalable FPGA Architecture for Randomly Connected Networks of Hodgkin-Huxley Neurons

et al. 2018

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“…In previous studies, FPGAs have been frequently employed for the design of neuromorphic computing circuits [50] [51]. This technology can be used either for prototyping and delivering a sub-part of a greater system, or directly as the final chip design implementation.…”

Section: Fpgamentioning

confidence: 99%

Design Space Exploration of Hardware Spiking Neurons for Embedded Artificial Intelligence

2020

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A B S T R A C TMachine learning is yielding unprecedented interest in research and industry, due to recent success in many applied contexts such as image classification and object recognition. However, the deployment of these systems requires huge computing capabilities, thus making them unsuitable for embedded systems. To deal with this limitation, many researchers are investigating brain-inspired computing, which would be a perfect alternative to the conventional Von Neumann architecture based computers (CPU/GPU) that meet the requirements for computing performance, but not for energy-efficiency. Therefore, neuromorphic hardware circuits that are adaptable for both parallel and distributed computations need to be designed. In this paper, we focus on Spiking Neural Networks (SNNs) with a comprehensive study of information coding methods and hardware exploration. In this context, we propose a framework for neuromorphic hardware design space exploration, which allows to define a suitable architecture based on application-specific constraints and starting from a wide variety of possible architectural choices. For this framework, we have developed a behavioral level simulator for neuromorphic hardware architectural exploration named NAXT. Moreover, we propose modified versions of the standard Rate Coding technique to make trade-offs with the Time Coding paradigm, which is characterized by the low number of spikes propagating in the network. Thus, we are able to reduce the number of spikes while keeping the same neuron's model, which results in an SNN with fewer events to process. By doing so, we seek to reduce the amount of power consumed by the hardware. Furthermore, we present three neuromorphic hardware architectures in order to quantitatively study the implementation of SNNs. One of these architectures integrates a novel hybrid structure: a highly-parallel computation core for most solicited layers, and time-multiplexed computation units for deeper layers. These architectures are derived from a novel funnel-like Design Space Exploration framework for neuromorphic hardware.

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“…A large-scale spiking neural network accelerator, which is capable of simulating ~400 k AdExp neurons in real-time was proposed by Cheung et al ( 2016 ). A recent system, capable of simulating a fully connected network with up to 1440 Izhikevich neurons, was proposed in Pani et al ( 2017 ). We have previously presented a design framework capable of simulating 1.5 million LIF neurons in real time (Wang et al, 2014c ).…”

Section: Introductionmentioning

confidence: 99%

An FPGA-Based Massively Parallel Neuromorphic Cortex Simulator

2018

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This paper presents a massively parallel and scalable neuromorphic cortex simulator designed for simulating large and structurally connected spiking neural networks, such as complex models of various areas of the cortex. The main novelty of this work is the abstraction of a neuromorphic architecture into clusters represented by minicolumns and hypercolumns, analogously to the fundamental structural units observed in neurobiology. Without this approach, simulating large-scale fully connected networks needs prohibitively large memory to store look-up tables for point-to-point connections. Instead, we use a novel architecture, based on the structural connectivity in the neocortex, such that all the required parameters and connections can be stored in on-chip memory. The cortex simulator can be easily reconfigured for simulating different neural networks without any change in hardware structure by programming the memory. A hierarchical communication scheme allows one neuron to have a fan-out of up to 200 k neurons. As a proof-of-concept, an implementation on one Altera Stratix V FPGA was able to simulate 20 million to 2.6 billion leaky-integrate-and-fire (LIF) neurons in real time. We verified the system by emulating a simplified auditory cortex (with 100 million neurons). This cortex simulator achieved a low power dissipation of 1.62 μW per neuron. With the advent of commercially available FPGA boards, our system offers an accessible and scalable tool for the design, real-time simulation, and analysis of large-scale spiking neural networks.

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An FPGA Platform for Real-Time Simulation of Spiking Neuronal Networks

Cited by 70 publications

References 44 publications

A Scalable FPGA Architecture for Randomly Connected Networks of Hodgkin-Huxley Neurons

A Scalable FPGA Architecture for Randomly Connected Networks of Hodgkin-Huxley Neurons

Design Space Exploration of Hardware Spiking Neurons for Embedded Artificial Intelligence

An FPGA-Based Massively Parallel Neuromorphic Cortex Simulator

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