An hierarchical VLSI neural network architecture

Mason, R.; Robertson, William; Pincock, D.

doi:10.1109/4.109562

Cited by 11 publications

(5 citation statements)

References 3 publications

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“…58. The main goal of this study is to show a prototype of a chip that presents hierarchical connectivity similar to that observed in biological neural networks.…”

Section: Pcnns For Hardware Implementationmentioning

confidence: 99%

A Survey of Partially Connected Neural Networks

Elizondo

Fiesler

1997

Int. J. Neur. Syst.

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Almost all artificial neural networks are by default fully connected, which often implies a high redundancy and complexity. Little research has been devoted to the study of partially connected neural networks, despite its potential advantages like reduced training and recall time, improved generalization capabilities, reduced hardware requirements, as well as being a step closer to biological reality. This publication presents an extensive survey of the various kinds of partially connected neural networks, clustered into a clear framework, followed by a detailed comparative discussion. * Int. J. Neur. Syst. 1997.08:535-558. Downloaded from www.worldscientific.com by FLINDERS UNIVERSITY LIBRARY on 02/03/15. For personal use only. Int. J. Neur. Syst. 1997.08:535-558. Downloaded from www.worldscientific.com by FLINDERS UNIVERSITY LIBRARY on 02/03/15. For personal use only.

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“…58. The main goal of this study is to show a prototype of a chip that presents hierarchical connectivity similar to that observed in biological neural networks.…”

Section: Pcnns For Hardware Implementationmentioning

confidence: 99%

A Survey of Partially Connected Neural Networks

Elizondo

Fiesler

1997

Int. J. Neur. Syst.

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“…The multiplier, including the offset, can be modeled as (9) where is a multiplication constant and , , and are the offsets. These offsets can be canceled, using four combinations of input signal polarity, as follows: (10) Then (11) In Fig. 9, and are nonoverlapping clocks.…”

Section: Circuit Designmentioning

confidence: 99%

“…Using clocks and , the switches at the multiplier input interchange the differential input line and the actual input to the multiplier becomes . At the end of the fourth phase, the integrator contains the offset canceled multiplication, as in (11). A folded CMOS Gilbert multiplier [13] is used.…”

Section: Circuit Designmentioning

confidence: 99%

A flexible and expendable neuroimage processor architecture

Han

Sánchez-Sinencio

1999

IEEE Trans. Circuits Syst. I

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An analog versatile neuroimage processor (VNIP) architecture is proposed here. VNIP can process various types of neural network and image processing structures, without any hardware modification. The structure allows unlimited expansion of network size and the compensation of process variation. The proof-of-concept chip is implemented, using a combination of continuous-time multiplier and switched-capacitor techniques. The throughput is 12 210 6 synapses/s 1 mm 2 and the energy consumption is 10 09 J/synapse. A test chip was fabricated, using a 1.2-m double-poly CMOS process and tested, verifying the flexibility and expandability of the architecture.

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“…Murre et al [32], [33] point out that there is an abundance of evidence supporting modularity as an organizing principle in the brain, and that modular neural networks are not only most realistic from the implementation point of view, but that they may also be favored from a biological perspective [34]- [38]. This issue has been considered by several researchers [4], [5], [9]- [11]. We have developed the digital VLSI BAM architecture aiming these desired characteristics, especially on-chip weight storage and high modularity.…”

Section: Introductionmentioning

confidence: 97%

A parallel processing VLSI BAM engine

Hasan

Siong

1997

IEEE Trans. Neural Netw.

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In this paper emerging parallel/distributed architectures are explored for the digital VLSI implementation of adaptive bidirectional associative memory (BAM) neural network. A single instruction stream many data stream (SIMD)-based parallel processing architecture, is developed for the adaptive BAM neural network, taking advantage of the inherent parallelism in BAM. This novel neural processor architecture is named the sliding feeder BAM array processor (SLiFBAM). The SLiFBAM processor can be viewed as a two-stroke neural processing engine, It has four operating modes: learn pattern, evaluate pattern, read weight, and write weight. Design of a SLiFBAM VLSI processor chip is also described. By using 2-mum scalable CMOS technology, a SLiFBAM processor chip with 4+4 neurons and eight modules of 256x5 bit local weight-storage SRAM, was integrated on a 6.9x7.4 mm(2) prototype die. The system architecture is highly flexible and modular, enabling the construction of larger BAM networks of up to 252 neurons using multiple SLiFBAM chips.

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An hierarchical VLSI neural network architecture

Cited by 11 publications

References 3 publications

A Survey of Partially Connected Neural Networks

A Survey of Partially Connected Neural Networks

A flexible and expendable neuroimage processor architecture

A parallel processing VLSI BAM engine

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