Proceedings of the 43rd Annual Conference on Design Automation - DAC '06 2006
DOI: 10.1145/1146909.1147100
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An IC manufacturing yield model considering intra-die variations

Abstract: In deep submicron feature sizes continue to shrink aggressively beyond the natural capabilities of the 193 nm lithography used to produce those features thanks to all the innovations in the field of resolution enhancement techniques (RET). With reduced feature sizes and tighter pitches die level variations become an increasingly dominant factor in determining manufacturing yield. Thus a prediction of designspecific features that impact intra-die variability and correspondingly its yield is extremely valuable a… Show more

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Cited by 16 publications
(21 citation statements)
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“…Experiments are performed on large testcases, each of which has 360K variation locations. Compared to [2], which is the only previous work to the best of our knowledge, the OPCA based method can reduce the error on yield estimation from 17.1% − 21.1% to 1.3% − 2.8% with 4.6× speedup. The HAQ technique can reduce the error to 4.1% − 5.6% with 6 × −9.4× speedup.…”
Section: Introductionmentioning
confidence: 92%
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“…Experiments are performed on large testcases, each of which has 360K variation locations. Compared to [2], which is the only previous work to the best of our knowledge, the OPCA based method can reduce the error on yield estimation from 17.1% − 21.1% to 1.3% − 2.8% with 4.6× speedup. The HAQ technique can reduce the error to 4.1% − 5.6% with 6 × −9.4× speedup.…”
Section: Introductionmentioning
confidence: 92%
“…The variation and yield models in this work are based on the case of metal thickness like in [2]. With small modifications, they can be applied to other cases, such as sequential timing yield.…”
Section: Variation and Yield Modelmentioning
confidence: 99%
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