An ILP based hierarchical global routing approach for VLSI ASIC design

Abstract

The use of integrated circuits in high-performance computing, telecommunications, and consumer electronics has been growing at a very fast pace. The level of integration as measured by the number of logic gates in a chip has been steadily rising due to the rapid progress in processing and interconnect technology. The interconnect delay in VLSI circuits has become a critical determiner of circuit performance. As a result, circuit layout is starting to play a more important role in today's chip designs. Global routing is one of the key sub-problems of circuit layout which involves finding an approximate path for the wires connecting the elements of the circuit without violating resource constraints. In this paper, several integer programming (ILP) based global routing models are fully investigated and explored. The resulting ILP problem is relaxed and solved as a linear programming (LP) problem followed by a rounding heuristic to obtain an integer solution. Experimental results obtained show that the proposed combined WVEM (wirelength, via, edge capacity) model can optimize several global routing objectives simultaneously and effectively. In addition, several hierarchical methods are combined with the proposed flat ILP based global router to reduce the CPU time by about 66% on average for edge capacity model (ECM).

GRIP: Global Routing via Integer Programming

“…The work [6] additionally considers a number of different objectives besides wirelength or overflow. The paper [32] builds on the work of [6], by describing different "heirarchical" approaches, where the routing problems are solved either "top-down" or "bottom-up." Computational results are given for chips with up to around 25,000 cells and nets.…”

“…However, this solution fixing when increasing the box size may lead to a degradation in solution quality. The work [32] proposes a hierarchical IP approach that first solves a small IP to plan the routing of the longest nets. However, the impact of the shorter nets is neglected.…”

“…Alternatively, some of the concurrent techniques that are "optimization-centric" such as those based on integer programming have typically been able to generate good solutions for moderate-sized problem instances. [7], [32], [4], [25], [6], [29], [17]. Procedures based on a hybrid combination of sequential and concurrent approaches are also proposed [10] to explore the solution quality and runtime tradeoff.…”

A Multilevel Congestion-Based Global Router

“…The mathematical program selects the trees that optimize a given objective while obeying the routing constraints; so ordering problems are avoided. Because of the advances in mathematical programming solvers, several concurrent global routers have been proposed recently [8,15,16]. BoxRouter [8] is an ILP-based router that uses progressive box expansion to formulate a sequence of ILPs that incrementally route the circuit.…”

“…Sidewinder [15] is a flat router that moderates the ILP size by only selecting two candidate trees from a potentially very large group of initial candidates. Multiobjective Router, presented in [16], has a variety of routing objectives to choose from including routing the maximum number of two-pin subnets without creating overflow.…”