An impedance-matching technique for increasing the bandwidth of microstrip antennas

Abstract

Spiral inductors with various metal fill-patterns under the spiral is fabricated with SOI CMOS technology and characterized up to 49 GHz. The impact of the fill on the inductor characteristics is found to be very small and changes can be attributed to the increase of parasitic capacitance. A simple model is proposed that can accurately estimate the increase of capacitance. A simple model is proposed that can accurately estimate the increase of capacitance by the fill. Design guidelinesfor optimizing fill patterns are recommended. © 2003 Wiley Periodicals, Inc. Microwave Opt Technol Lett 36: 462-465, 2003; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop. 10790 Key words: spiral inductors; fill patterns; RF CMOS; silicon-on-insulator; RF inductors INTRODUCTIONIn order to maintain the uniformity and reproducibility of the etching and chemical mechanical polishing (CMP) processes in today's deep sub-micron CMOS technology, incorporation of fill patterns [1,2] in the layout, especially on metal layers, is becoming a standard practice. In analog and RF CMOS circuits, spiral inductors are widely used. However, having conducting fill patterns under a spiral inductor has been considered undesirable based on the intuition that they can alter the field distribution and, therefore, the characteristics of the inductors. Although spiral inductors have been studied extensively for performance optimization [3], analysis of the effects of fill patterns on the same metal layer as the inductor was reported only recently [4,5]. In this work, the effect of fill at metal levels under the spirals, with various configurations on the inductors, is studied. Based on the test results, simple guidelines are provided for the design of the fill. INDUCTORS WITH FILL PATTERNSThe inductors were fabricated using a standard SOI process with three levels of metal [6]. The results reported here should also be applicable to the standard bulk-Si CMOS because the only difference is the presence of a 200-nm-thick buried oxide on top of the 10⍀-cm resistivity Si substrate. The thickness of the Al metal and the oxide between metal layers is 0.6 m. The thickness of the oxide between metal-1 and the Si substrate, including the buried oxide of the SOI wafer, is approximately 0.9 m. Only metal-3 is used as the inductor spiral. Floating fill, consisting of isolated patterns with no connection to ground, is chosen because its capacitance is smaller than that of grounded fill. Furthermore, it can be more easily generated as an add-on to the layout automatically. The purpose of this work is to examine the effect of fill; no attempt was made to optimize the fill patterns. All inductors have 5 turns with an inner diameter of 18 m, and the width and the spacing of the spiral lines are 3 m and 1 m, respectively. The inductor is configured as a one-port device with the center tap connected to ground. As shown in Figure 1, one type of fill consists of squares with a checkerboard arrangement. The side of the square and th...

Broadband Modified Rectangular Microstrip Patch Antenna Using Stepped Cut at Four Corners Method

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“…It is evident that the calculated matching level is increased by using a reactive impedance matching network [9,10,11]. Ideally, this compensation network could transform the frequency dependent complex antenna impedance Z in to a pure real resistance Z 0 over a large bandwidth as required as shown in Fig.…”

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