An implementation of Auto-Memoization mechanism on ARM-based superscalar processor

Abstract

We have proposed a processor called Auto Memoization Processor which is based on computation reuse. Un til now, we have implemented the auto-memoization mechanism on a single-issue non-pipelined SPARC processor and studied the processor. The processor dynamically detects functions and loop iterations as reusable blocks, and memoizes them automatically.In addition, the processor can apply computation reuse to the blocks with a little reuse overhead. However, the fine evaluation result of the processor may not guarantee enough practicality. This is because instead of such a simple architecture, superscalar architectures are now widely used for generic processors for PCs, embedded processors, and other various processors. Hence, we examine problems which will be caused in the case of implementing the auto-memoization mechanism on an ARM based superscalar processor and design the ARM-based Auto Memoization Processor. For example, one of such problems is that pipeline stalls are caused because of the reuse overhead. To solve this problem, we implement a mechanism for overlapping the reuse overhead and the pipeline execution of the processor. The evaluation result with SPEC CPU95 benchmark suite shows that the ARM-based Auto-Memoization Processor can also achieve speed-up as well as the previous SPARC-based Auto-Memoization Processor. In this paper, we describe the implementation and the evaluation result of the ARM-based Auto-Memoization Processor.

Approximate function memoization

“…Literature 6 provides a clear distinction between them. But when we compare CR [7][8][9][10][11][12][13][14][15][16]30 and MZ, [17][18][19][20][21][22][23][24][25][26][27][28][29]35,36 we could not found sufficient difference among these two. Conceptually, CR refers to "reusing previously computed (buffered) results if same input appears again," and MZ refers to "storing the current result and reuse in future if similar input appears again.…”

DF‐DTM: Dynamic Task Memoization and reuse in dataflow

“…DTM is a reuse technique that operates on traces of instructions and is often implemented on top of Von Neumann‐based superscalar architectures, with further studies that include speculative execution . Speculative execution often improves the reuse rate of traces, because it enables reuse based on speculative values for input operands.…”

“…15 The size of each operation, ie, the reuse granularity, can vary from a single instruction 16 to groups of instructions, such as functions, 11 expressions, 17 basic blocks, 18 sub-blocks, 19 or traces. 20 DTM 10 is a reuse technique that operates on traces of instructions and is often implemented on top of Von Neumann-based superscalar architectures, [16][17][18][19][20][21][22][23][24] with further studies that include speculative execution. [25][26][27][28] Speculative execution often improves the reuse rate of traces, because it enables reuse based on speculative values for input operands.…”

DTM@GPU: Characterizing and evaluating trace redundancy in GPU

“…22 Moreover, other studies have implemented similar memoization schemes into ARM-based superscalar processors. [23][24][25][26] Some works have also explored the reuse of computation in the GPU domain. 27 For instance, redundant fragment shader executions have been reused on a mobile GPU through hardware memoization.…”