An implementation of CMOS design for testability techniques for non stuck-at faults

Abstract

The paper presents an experimental analysis of DFT techniques used to detect the presence of faulty resistive paths throughout CMOS ICs. Current monitoring, delay fault testing and new design for testability (DFT) techniques are compared by means of a chip designed ad hoc, that allows to simulate via hardware the presence of resistive bridgings within standard functional blocks. The results presented in this work suggest that specific DFT techniques offer considerable advantages over more conventional approaches.