An Implementation Technique of Multi-Cycled Arithmetic Functions For a Dynamically Reconfigurable Processor

Miyata, Miwa; Tsuchiya, Hideyuki; Shibata, Yuichiro; Oguri, Kazuta

doi:10.1109/fpl.2006.311291

Cited by 1 publication

(1 citation statement)

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“…While some of early reconfigurable systems such as Garp [7] and NAPA [6] had already supported programing environment based on C languages, some recent systems like DRP [10] take a hybrid approach of a compiler and high-level synthesis. However, the role of programmers is still important on optimization issues such as memory allocation for parallelism and DMA transfer [14], [9]. While novel programming models such as CHiMPS [13] and xPilot [5] have been proposed, this work is the first attempt of a fine-grained multithread model for reconfigurable systems as far as the authors know.…”

Section: Related Workmentioning

confidence: 98%

Implementation of a programming environment with a multithread model for reconfigurable systems

Dohi

Shibata

Hamada

et al. 2010

SIGARCH Comput. Archit. News

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Reconfigurable systems are known to be able to achieve higher performance than traditional microprocessor architecture for many application fields. However, in order to extract a full potential of the reconfigurable systems, programmers often have to design and describe the best suited code for their target architecture with specialized knowledge. The aim of this paper is to assist the users of reconfigurable systems by implementing a translator with a multithread model. The experimental results show our translator automatically generates efficient performance-aware code segments including DMA transfer and shift registers for memory access optimization.

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