An improved algorithm for TAM optimization to reduce test application time in core based SoC

Parmar, Harikrishna; Mehta, Usha

doi:10.1109/wiecon-ece.2015.7443963

Cited by 2 publications

(5 citation statements)

References 18 publications

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“…If we assign the cores to channel in such a way that, parallel testing of core is maximum and the idle channel width is minimum, then the test time is reduced effectively. In [19], we have presented the algorithm for the effective utilization of idle channel width to determine the width of the TAM bus assigned to the individual core and improved partition strategy for the TAM bus. The algorithm also focuses on improved core assignment to the partitioned TAM bus and test scheduling.…”

Section: Motivationmentioning

confidence: 99%

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ILP Based Power-Aware Test Time Reduction Using On-Chip Clocking in NoC Based SoC

Parmar

Mehta

2019

JLPEA

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Network-on-chip (NoC) based system-on-chips (SoC) has been a promising paradigm of core-based systems. It is difficult and challenging to test the individual Intellectual property IP cores of SoC with the constraints of test time and test power. By reusing the on-chip communication network of NoC for the testing of different cores in SoC, the test time and test cost can be reduced effectively. In this paper, we have proposed a power-aware test scheduling by reusing existing on-chip communication network. On-chip test clock frequencies are used for power efficient test scheduling. In this paper, an integer linear programming (ILP) model is proposed. This model assigns different frequencies to the NoC cores in such a way that it reduces the test time without crossing the power budget. Experimental results on the ITC’02 benchmark SoCs show that the proposed ILP method gives up to 50% reduction in test time compared to the existing method.

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Section: Motivationmentioning

confidence: 99%

“…The algorithm also focuses on improved core assignment to the partitioned TAM bus and test scheduling. The limitation of the algorithm in [19] is that it is exhaustive in nature and has a long execution time for big SoCs.…”

Section: Motivationmentioning

confidence: 99%

ILP Based Power-Aware Test Time Reduction Using On-Chip Clocking in NoC Based SoC

Parmar

Mehta

2019

JLPEA

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“…Core test wrapper makes the interface between design under test (core) and its environment. It interfaces the input-output of a core to the rest of the IC and the test access mechanism [2,3].…”

Section: Introductionmentioning

confidence: 99%

“…It gives the detail about the order in which various cores are tested. It also ensures that there is no resource conflict among cores [3].…”

Section: Introductionmentioning

confidence: 99%

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Test Time Reduction Using Power-Aware Dynamic Clock Allocation to Scan Vectors

Parmar

Mehta

2020

Lecture Notes in Electrical Engineering

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As circuit size increases with scale down in technology, the time required to test the circuits also increases. Scheduling of the cores is a very effective technique to reduce the test time of a system-on-chip (SoC) in the given power budget. As the frequency is relative to the power and the test time, by controlling the test clock frequency, the power consumption and the test time per core can be adjusted to yield an optimal solution to the test scheduling problem. In traditional methods, the fixed test clock frequency is applied to all the test vectors of a given core in case of power-aware test scheduling. Whereas in the proposed plan, a power-aware dynamic frequency allocation is done to individual scan vector of the core. Session-based test scheduling scheme is implemented to reduce test time. Results show the improvement up to 58% with session-based test scheduling is achieved over the existing solution for the benchmark SoCs with minor bit and area overhead.

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An improved algorithm for TAM optimization to reduce test application time in core based SoC

Cited by 2 publications

References 18 publications

ILP Based Power-Aware Test Time Reduction Using On-Chip Clocking in NoC Based SoC

ILP Based Power-Aware Test Time Reduction Using On-Chip Clocking in NoC Based SoC

Test Time Reduction Using Power-Aware Dynamic Clock Allocation to Scan Vectors

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