An improved CMOS ring oscillator PLL with less than 4ps RMS accumulated jitter

Williams, S.; Thompson, H. W.; Hufford, M.; Naviasky, E.

doi:10.1109/cicc.2004.1358761

Cited by 33 publications

(17 citation statements)

References 2 publications

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“…The output of the loop filter serves as the fine control voltage. A separate frequency-tracking loop (referred to as the coarse loop hereafter) integrates the voltage across the loop filter capacitor and drives the VCO toward frequency lock [22], [23]. The integrator is implemented as a first order filter.…”

Section: Phase-locked Loop Designmentioning

confidence: 99%

A Wide-Tracking Range Clock and Data Recovery Circuit

Hanumolu

Wei

Moon

2008

IEEE J. Solid-State Circuits

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Abstract-A hybrid analog-digital quarter-rate clock and data recovery circuit (CDR) that achieves a wide-tracking range and excellent frequency and phase tracking resolution is presented in this paper. A split-tuned analog phase-locked loop (PLL) provides eight equally spaced phases needed for quarter-rate data recovery and the digital CDR loop adjusts the phase of the PLL output clocks in a precise manner to facilitate plesiochronous clocking. The CDR employs a second-order digital loop filter and combines delta-sigma modulation with the analog PLL to achieve sub-picosecond phase resolution and better than 2 ppm frequency resolution. A test chip fabricated in a 0.18 m CMOS process achieves BER 10 and consumes 14 mW power while operating at 2 Gb/s. The tracking range is greater than 5000 ppm and 2500 ppm at 10 kHz and 20 kHz modulation frequencies, respectively, making this CDR suitable for systems employing spread-spectrum clocking.Index Terms-Clock and data recovery, phase-locked loop (PLL), spread-spectrum clocking, digital phase interpolation, delta-sigma.

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Section: Phase-locked Loop Designmentioning

confidence: 99%

A Wide-Tracking Range Clock and Data Recovery Circuit

Hanumolu

Wei

Moon

2008

IEEE J. Solid-State Circuits

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“…The high-Q LC VCO, however, suffers from a narrow tuning range. The trade-off between noise performance and tuning range can be overcome by having multiple varactors [4][5] or by adopting a dual-path control [6][7][8][9][10][11][12][13]. Fig.…”

Section: Bandwidth Variationmentioning

confidence: 99%

“…Furthermore, since the gain of the analog coarse-tuning path is much higher than that of the fine-tuning path, any coupling due to supply noise or substrate noise can affect the VCO noise performance. Secondly, the dual-path control often requires a PLL topology change such as the introduction of an additional voltage node from the loop filter [6][7][8][9] or an additional phase detector (or charge pump) [10][11][12]. Lastly, for stability reason, the coarsetuning control loop must have much narrower bandwidth than the PLL bandwidth, increasing the area of the stabilizing capacitor in the coarse-tuning path.…”

Section: Bandwidth Variationmentioning

confidence: 99%

“…Since PCIe2 operates at twice the data rate of PCIe, the jitter budget is tighter, demanding random jitter (RJ) of less than 1.4 ps. The PLL bandwidth is specified by the standard, for example, it must be within a range of [8][9][10][11][12][13][14][15][16] MHz in the case where up 3-dB peaking is allowed in jitter transfer function. As the loop para meters of the on-chip PLL vary a lot over process and temperature, a means of achieving uniform bandwidth to meet PCIe2 specifications is needed.…”

Section: Introductionmentioning

confidence: 99%

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A Continuously Tunable LC-VCO PLL with Bandwidth Linearization Techniques for PCI Express Gen2 Applications

Rhee¹,

Ainspan²,

Friedman³

et al. 2008

JSTS:Journal of Semiconductor Technology and Science

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Abstract-This paper describes bandwidth linearization techniques in phase-locked loop (PLL) design for common-clock serial link applications. Utilizing a continuously tunable single-input dual-path LC VCO and a constant-gain phase detector, a proposed architecture is well suited to implementing PLLs that must be compliant with standards that specify minimum and maximum allowable bandwidths such as PCI Express Gen2 or FB-DIMM applications. A prototype 4.75 to 6.1-GHz PLL is implemented in 90-nm CMOS. Measurement results show that the PLL bandwidth and random jitter (RJ) variations are well regulated and that the use of a differentially controlled dualpath VCO is important for deterministic jitter (DJ) performance.

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“…1(c). This architecture has been implemented using both ring VCOs [1,2] and LC-VCOs [3]. The VCO is controlled by two varactors: a small varactor tuned by a fine control voltage V ctrl and a large varactor tuned by a coarse control voltage V C .…”

Section: Frequency Synthesizer Architecturesmentioning

confidence: 99%

A 4.2 GHz PLL Frequency Synthesizer with an Adaptively Tuned Coarse Loop

Hanumolu

Mayaram

et al. 2007

2007 IEEE Custom Integrated Circuits Conference

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A 4.2 GHz integer-N PLL frequency synthesizer for WLANs is described. An analog split tuned LC-VCO is controlled by coarse and fine loops to achieve both a large frequency tuning range and a small VCO gain. An averaging varactor is employed to reduce the amplitude sensitivity of the varactor, thereby reducing the AM-to-FM noise conversion. A new adaptively tuned switched capacitor integrator is used in the coarse loop for a fast lock time. The prototype test chip in a 0.13-µm CMOS process has a measured phase noise of -110dBc/Hz at 1 MHz offset, and a settling time of 50 µs. I. IntroductionThe design of PLL frequency synthesizers is a difficult task due to the conflicting requirements of small integrated phase noise, fast settling time, small spur levels, and low power consumption. This is made even more challenging due to increased process, voltage, and temperature (PVT) variations in scaled CMOS processes. For example, the designed frequency tuning range must be much wider than the specifications in order to overcome the PVT variations.In this paper, we evaluate architectural choices for wide tuning range frequency synthesizers. This leads to the development of an analog split-tuned LC-VCO based 4.2 GHz PLL frequency synthesizer with a wide tuning range and a small VCO gain. In addition, AM-to-FM phase noise conversion is reduced with the use of an averaging varactor and a fast settling time is achieved with a new adaptively tuned switched capacitor integrator.The paper is organized as follows. In Section II, frequency synthesizer architectures for wide tuning range are compared and an analog split-tuned LC-VCO based architecture is identified as a suitable candidate. This is followed by a linear analysis of the split-tuned PLL in Section III and provides guidance on the selection of the loop parameters. The circuit design is presented in Section IV, followed by measurement results in Section V. The paper is concluded in Section VI.

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An improved CMOS ring oscillator PLL with less than 4ps RMS accumulated jitter

Cited by 33 publications

References 2 publications

A Wide-Tracking Range Clock and Data Recovery Circuit

A Wide-Tracking Range Clock and Data Recovery Circuit

A Continuously Tunable LC-VCO PLL with Bandwidth Linearization Techniques for PCI Express Gen2 Applications

A 4.2 GHz PLL Frequency Synthesizer with an Adaptively Tuned Coarse Loop

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