An improved delay compensation technique for digital clock recovery loops

Abstract

It is well known that time delays often cause instability in a closed-loop system forcing it to operate under sub-optimal conditions. Timing recovery systems encountered in today's communications systems are an example of such systems due to the latency caused, on one side, by the always increasing data rate and, on the other, by the complexity of the signal processing employed. It's possible to modify the topology of a Phase Locked Loop (PLL) in order to reduce the effects that latency has on the loop stability and dynamics. This paper proposes a new topology which differs from previous work in that it's characterized by a closed-loop transfer function which is the product of a delay term and a rational function in z and, at the same time, achieves zero steady-state error in response to a frequency step.

Design and FPGA-Implementation of a High Performance Timing Recovery Loop for Broadband Communications

“…It is known that introducing new elements in the loop that increase the total loop delay changes its dynamics [4] (its type-II behaviour may be lost), so sometimes it is nonsense to design using the T L and B L equations given in 4.a and 4.b. Figure 3a shows the unity step response of a loop designed for a lock-up time of 1,000 samples in which five different loop delays are introduced.…”

“…One author [4] has proposed changes in the architecture of the loop trying to compensate for the effect of the loop delays. Nonetheless this compensation technique is only applicable to the delays concentrated in a part of the circuit, making this technique not suitable for pipelined circuits.…”