An Improved Matrix Generation Framework for Thermal Aware Placement in VLSI

Abstract

Since hotspots and temperature gradients are reliability and performance-critical issues in processors, thermal awareness finds a vital place in the processor design cycle. Incorporating thermal awareness at the level of physical design, this work proposes a new, fast, and efficient thermal aware placement algorithm called the Thermal Aware Matrix Placement Optimizer (TAMPO) for gate arrays. The algorithm TAMPO is composed of the following components: an improved heat diffusion aware cell arrangement technique called the Initial Matrix Generator (IMaGe), a unique stochastic thermal model based on a thermally improved interpretation of the well known Matrix Synthesis Problem (MSP) and a Simulated Annealing (SA) engine for finding the global optimum solution. TAMPO targets to reduce the peak temperature while maintaining improved values of temperature gradients and the standard deviation in cell temperature with respect to the average chip temperature. This work also presents a methodology, the Co-optimized TAMPO, which extends the concept of TAMPO to simultaneously optimize the thermal attributes and the wirelength of a chip. The proposed algorithms realize a placement in matrix arrangement and upon experimentation on the ISCAS89 benchmark circuits encouraging results have been obtained.