An Improved Non-CSD 2-Bit Recursive Common Subexpression Elimination Method to Implement FIR Filter

Abstract

The number of adders and critical paths in a multiplier block of a multiple constant multiplication based implementation of a finite impulse response (FIR) filter can be minimized through common subexpression elimination (CSE) techniques. A two-bit common subexpression (CS) can be located recursively in a noncanonic sign digit (CSD) representation of the filter coefficients. An efficient algorithm is presented in this paper to improve the elimination of a CS from the multiplier block of an FIR filter so that it can be realized with fewer adders and low logical depth as compared to the existing CSE methods in the literature. Vinod and others claimed the highest reduction in the number of logical operators (LOs) without increasing the logic depth (LD) requirement. Using the design examples given by Vinod and others, we compare the average reduction in LOs and LDs achieved by our algorithm. Our algorithm shows average LO improvements of 30.8%, 5.5%, and 22.5% with a comparative LD requirement over that of Vinod and others for three design examples. Improvement increases as the filter order increases, and for the highest filter order and lowest coefficient width, the LO improvements are 70.3%, 75.3%, and 72.2% for the three design examples.

A Design of Low Latency Random Access Preamble Detector for LTE Uplink Receiver

“…A 12 bit ADC is used and a 35-tap FIR filter is used for decimation filter. The filter is implemented efficiently using sub-expression elimination method [11]. The FFT/IFFT processor is 2048-pt pipelined FFT/IFFT processor so that it can handle back-to-back continuous input data.…”