An Improved Offset Min-Sum LDPC Decoding Algorithm for 5G New Radio

Tran-Thi, Bich Ngoc; Nguyen-Ly, Thien Truong; Hong, Hoa Nguyen; Hoang, Trang

doi:10.1109/isee51682.2021.9418782

Cited by 5 publications

(6 citation statements)

References 9 publications

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“…The HOMS is set with β = 0.5 and δ = 0.375 [19]. For comparison purposes, the performances of the NMS (1/α = 0.75) [14], OMS (β = 0.5) [14], IOMS ( γ = 0.875 and η = 0.5) [16], SMA-MSA ( α2 = 0.25 and γ = 0.75) [17], S2DS [18], and VOMS ( β = 0.5 and τ = 0.875) [19] algorithms are also evaluated.…”

Section: Performance Resultsmentioning

confidence: 99%

“…In an effort to improve this performance loss, numerous approaches have been presented in the state-of-the-art, including some well-known algorithms such as the Offset Min-Sum (OMS) and the Normalized Min-Sum (NMS) [14,15]. Moreover, several enhancements have been further proposed in the literature, such as the Improved Offset Min-Sum (IOMS) algorithm [16], the Second Minimum Approximation Min-Sum algorithm (SMA-MSA) [17], the Simplified 2-Dimensional Scaled (S2DS) algorithm [18], the Hybrid Offset Min-Sum (HOMS), and the Variable Offset Min-Sum (VOMS) algorithms [19].…”

Section: Introductionmentioning

confidence: 99%

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An FPGA Design with High Memory Efficiency and Decoding Performance for 5G LDPC Decoder

Tran-Thi,

Nguyen-Ly,

Hoang

2023

Electronics

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A hardware-efficient implementation of a Low-Density Parity-Check (LDPC) decoder is presented in this paper. The proposed decoder design is based on the Hybrid Offset Min-Sum (HOMS) algorithm. In the check node processing of this decoder, only the first minimum is computed instead of the first two minimum values among all the variable-to-check message inputs as in the conventional approach. Additionally, taking advantage of the unique structure of 5G LDPC codes, layered scheduling and partially parallel structures are employed to minimize hardware costs. Implementation results on the Xilinx Kintex UltraScale+ FPGA platform show that the proposed decoder can achieve a throughput of 2.82 Gbps for 10 decoding iterations with a 5G LDPC codelength of 8832 bits and a code rate of 1/2. Moreover, it yields a check node memory reduction of 10% with respect to the baseline and provides a hardware usage efficiency of 4.96 hardware resources/layer/Mbps, while providing a decoding performance of 0.15 dB better than some of the existing decoders.

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Section: Performance Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

An FPGA Design with High Memory Efficiency and Decoding Performance for 5G LDPC Decoder

Tran-Thi,

Nguyen-Ly,

Hoang

2023

Electronics

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“…Although Min-Sum decoding consumes fewer hardware resources than Belief-Propagation (known as the best decoding algorithm), error correction performance is not good enough because of the overestimation issue of checknode messages. To compensate for this overestimation, many approaches have been proposed in the literature, which aim to improve error correction capacity [27][28][29][30][31][32][33][34][35]. However, the limitation of these algorithms is the existing error-floor when the SNR is high.…”

Section: The Proposed Decoding Algorithmmentioning

confidence: 99%

“…This iterative process continuously proceeds until the correct codeword is successfully found or until the maximum number of iterations has been reached. Depending on the update rules that are used to compute check and variable-node messages, there are several message-passing decoding algorithms, such as Belief-Propagation (BP), Min-Sum (MS), and MS-based algorithms [27][28][29][30][31][32][33][34][35]. Although MS and MS-based algorithms have lower error correction capacity than BP, they are simpler and more suitable for hardware implementations.…”

Section: Introductionmentioning

confidence: 99%

“…A limitation of this IAMS decoding was that the error-floor occurred around Frame-Error-Rate (FER) of 10 −5 . The authors in [35] presented an Improved OMS (IOMS) algorithm by using a multiplication factor to modify the check node updating. Although, the IOMS showed a gain of 0.1 dB with respect to the conventional OMS decoder, the major disadvantage of this algorithm is that the BER still suffered from error-floor at BER of 10 −6 .…”

Section: Introductionmentioning

confidence: 99%

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Further Improvements in Decoding Performance for 5G LDPC Codes Based on Modified Check-Node Unit

Tran-Thi¹,

Nguyen-Ly²,

Hoang³

2023

RADIOENGINEERING

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One of the most important units of Low-Density Parity-Check (LDPC) decoders is the Check-Node Unit. Its main task is to find the first two minimum values among incoming variable-to-check messages and return check-tovariable messages. This block significantly affects the decoding performance, as well as the hardware implementation complexity. In this paper, we first propose a modification to the check-node update rule by introducing two optimal offset factors applied to the check-to-variable messages. Then, we present the Check-Node Unit hardware architecture which performs the proposed algorithm. The main objective of this work aims to improve further the decoding performance for 5 th Generation (5G) LDPC codes. The simulation results show that the proposed algorithm achieves essential improvements in terms of error correction performance. More precisely, the error-floor does not appear within Bit-Error-Rate (BER) of 10 -8 , while the decoding gain increases up to 0.21 dB compared to the baseline Normalized Min-Sum, as well as several state-ofthe-art LDPC-based Min-Sum decoders.

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