2012 IEEE International Conference on Circuits and Systems (ICCAS) 2012

DOI: 10.1109/iccircuitsandsystems.2012.6408341

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An improved power constrained simultaneous noise and input matched 2.45 GHz CMOS NB-LNA

Hamidreza Ameri Eshghabadi

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Farshad Eshghabadi

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Mohd Tafir Mustaffa

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et al.

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Cited by 7 publications

References 11 publications

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Design Considerations for Low Noise Amplifier

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2021

Inventive Systems and Control

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Design Considerations for Low Noise Amplifier

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2021

Inventive Systems and Control

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A high-gain Source degenerative Cascode LNA for Wi-MAX and W-CDMA applications at 3.5GHz

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et al. 2014

2014 International Conference on Control, Instrumentation, Communication and Computational Technologies (ICCICCT)

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This paper presents the design and simulation of High gain S ource degenerated Cascode LNA for Wi-max and W-CDMA applications at 3.5GHz. The design uses an enhanced cascade topology to attain improved forward gain and noise figure. Th is design includes lumped elements like inductor, capacitor and resistors to design input and output matching networks. The targeted narrow-band gain, impedance matching and noise figure are achieved at the 3.5GHz . Circuit has been designed Using standard UMC 0.18µm CMOS technology and simulated in the Cadence S pectre RF tool . Targeted narrowband gain, noise figure, are 25dB and 2dB respectively. The designed circuit exhibits narrow-band gain of 27.18 dB and noise figure of 1.7 dB with Input and output return loss of -17.57 dB and -29.21 dB respectively. Circuit operates from the supply voltage of 1.8V and draws a current of 6.39mA.

A review of LNA topologies for wireless applications

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et al. 2014

2014 2nd International Conference on Electronic Design (ICED)

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