An Improved Programming Model for Thread-Level Speculation

Loop Selection for Multilevel Nested Loops Using a Genetic Algorithm

“…e authors in [1,4,[33][34][35][36][37] obtained the profiling information that reflects the behavior of the program through multiple preexecution programs using the thread-level speculation technique in combination with the information on the program during preexecution, and then, the appropriate loop layer was selected for parallel execution based on the predicted performance. However, the dependence analysis ability of the hardware was limited, and thus, the Mathematical Problems in Engineering success rate of these techniques in stimulating multithreaded parallel execution in multilevel nested loops was not high [1,4,[33][34][35][36][37]. In [31,[38][39][40][41], a multilevel nested loop threadlevel parallelization scheme that combines static analysis and dynamic scheduling was adopted.…”

“…One approach is to use the multithread implementation technology of the underlying hardware, in which the appropriate loop layer is chosen for multithread parallelization with the assistance of the underlying hardware, e.g., the thread-level speculation (TLS) technique and the transactional memory (TM) technique. However, the dependency analysis capability of the underlying hardware is limited and lacks flexibility, which makes it difficult for the TLS technique to analyze the complex dependencies of the multilevel nested loops and thus is impossible to provide effective parallelism [1][2][3][4][5][6]. e hardware TM technique has limitations on the transactional size (transactional buffer) and duration (operating system events and disruptions can abort the transaction); therefore, when applied to the thread-level parallelism of nested loops, it often leads to overflow of the underlying hardware resources due to excessive granularity of the transaction itself, which ultimately manifests poor parallel performance [7][8][9][10][11][12].…”