An improved RNS Montgomery modular multiplier

Tongjie, Yang; Dai, Zibin; Yang, Xiaohui; Zhao, Qian

doi:10.1109/iccasm.2010.5622857

Cited by 5 publications

(6 citation statements)

References 10 publications

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“…The design in [4] proposed an RNS-based modular multiplier, improving on Bajard's work in [10]. The implementation in 0.18 μm CMOS technology shows a slightly lower latency than our proposed design.…”

Section: Comparisonmentioning

confidence: 86%

“…Modular multiplication (MM) is the fundamental operation of public-key cryptosystems such as Rivest-Shamir-Adleman (RSA) [1] and elliptic-curve cryptography (ECC) [2]. In recent years, MM in residue number system (RNS) has gained popularity due to its high-speed arithmetic operations on large numbers [3][4][5]. In RNS the large numbers are distributed across several small channels allowing concurrent fast arithmetic operations [6].…”

Section: Introductionmentioning

confidence: 99%

“…However, the work in [10] employs two different techniques for first and second base extensions allowing more freedom for optimisation. An improvement to this algorithm was proposed in [4], to construct a hardware architecture of an RNS-based modular multiplier. A modified ME algorithm for RNS is proposed in [16] and uses pre-computations to reduce the number of multiplications in the ME algorithm.…”

Section: Introductionmentioning

confidence: 99%

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65‐nm CMOS low‐energy RNS modular multiplier for elliptic‐curve cryptography

Asif¹,

Andersson²,

Rodrigues³

et al. 2017

IET Computers & Digital Techniques

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Modular multiplication (MM) is the main operation in cryptography algorithms such as elliptic-curve cryptography (ECC) and Rivest-Shamir-Adleman, where repeated MM is used to perform elliptic curve point multiplication and modular exponentiation, respectively. The algorithm for the proposed architecture is derived from the Chinese remainder theorem and performs MM completely within a residue number system (RNS). Moreover, a 40-channel RNS moduli-set is proposed for this architecture to benefit from the short-channel width of the RNS moduli-set. The throughput of the architecture is enhanced by pipelining and pre-computations. The proposed architecture is fabricated as an ASIC using 65-nm CMOS technology. The measurement results are obtained for energy dissipation at different voltage levels from 0.43 to 1.25 V. The maximum throughput of the proposed design is 1037 Mbps while operating at a frequency of 162 MHz with an energy dissipation of 48 nJ. The proposed architecture enables the construction of low-voltage and energy-efficient ECCs.

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Section: Comparisonmentioning

confidence: 86%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

65‐nm CMOS low‐energy RNS modular multiplier for elliptic‐curve cryptography

Asif¹,

Andersson²,

Rodrigues³

et al. 2017

IET Computers & Digital Techniques

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“…Other algorithms that employ MRC also perform worse. For example, the work in [TjZbXHQj10] requires 2L 2 + 5L modular multiplications while the work in [BDK98] is a predecessor of [BI04], which also performs worse, as shown in Table 5.3. This is also due to the simplified version of MRC employed in this work that requires L − 2 multiplication to implement (2.32), while [BDK98] requires L L−1 2 multiplications for the same conversion to implement (2.31) [BDK98,TjZbXHQj10].…”

Section: Comparisons With Rns Implementationsmentioning

confidence: 99%

“…Exponentiation execution times were calculated assuming that a single exponentiation requires 2n + 2 Montgomery multiplications. Works in [LH08a,Gui10,TjZbXHQj10] provide results for precisions up to 512-bit, thus direct comparisons are infeasible. The works in [BDK98,Gro01] were also not included since no experimental results are presented.…”

Section: Area-time-power Comparisonsmentioning

confidence: 99%

Versatile architectures for cryptographic systems

Schinianakis¹

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We live in a world that demands more and more connectivity. Our everyday life is dominated by an overwhelming amount of information that needs to be controlled and maintained. Everyday transactions that few years ago required our physical existence, have been replaced by electronic applications. Users may now use friendly, fast and safe interfaces to perform easily numerous tasks, varying from money transfers using the web and remote health checks to e-learning and e-commerce. Being exposed in an unprecedented number of threats and frauds, safe connectivity for all network-based systems has now become a predicate necessity. The science of cryptography provides the necessary tools and means towards this direction. Cryptographic hardware and software play now a dominant role in e-commerce, mobile phone communications, military applications, private emails, digital signatures for e-commerce, ATM cards, web banking, maintenance of health records and so on. This doctoral thesis approaches the problem of designing versatile architectures for cryptographic hardware. By the term versatile we define hardware architectures capable of supporting a variety of arithmetic operations and algorithms useful in cryptography, with no need to reconfigure the internal interconnections of the integrated circuit. I owe my deepest gratitude to my supervisor, Professor Thanos Stouraitis, for his excellent guidance throughout the 8 years of my Ph.D. studies. I consider myself more than lucky to have collaborated with him in the development of this doctoral thesis. I would like to gratefully thank him not only as a supervisor, but also as a friend. Thanos stood for me as a real source of inspiration, an example of out-of-the-box thinking, a paradigm of devotion and faith to hard work. This thesis would not have been possible without his exemplary support and his continuous and close supervision. During all those years, I had the opportunity to collaborate with several remarkable people, who influenced my work and provided me with invaluable help in my research. I am grateful to my friends Dr. Athanasios Kakarountas, and Dr. Charalampos Michail for the collaboration and cooperation during the first years of my Ph.D. studies. The roots of this thesis share a lot of common thoughts and efforts. I would also like to thank Mrs. Fotopoulou Eleni and Mr. Ferentinos Aris for our collaboration and all the fun moments we had in the Digital Signal & Image Processing Lab. Furthermore, I owe my deepest gratitude to my co-supervisors Prof. Odysseas Koufopavlou and Prof. Christos Zaroliagis, for the valuable comments, guidance and support during the preparation of this dissertation. Last, but not least, my family and friends deserve my deepest gratitude for their support and belief in me throughout those 8 years. I sincerely believe that this work would not have been as successful without them.

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Highly Parallel Modular Multiplier for Elliptic Curve Cryptography in Residue Number System

Asif

Kong

2016

Circuits Syst Signal Process

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An improved RNS Montgomery modular multiplier

Cited by 5 publications

References 10 publications

65‐nm CMOS low‐energy RNS modular multiplier for elliptic‐curve cryptography

65‐nm CMOS low‐energy RNS modular multiplier for elliptic‐curve cryptography

Versatile architectures for cryptographic systems

Highly Parallel Modular Multiplier for Elliptic Curve Cryptography in Residue Number System

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