An improved RNS reverse converter for the {2&lt;sup&gt;2n&amp;#x002B;1&lt;/sup&gt;&amp;#x2212;1, 2&lt;sup&gt;n&lt;/sup&gt;, 2&lt;sup&gt;n&lt;/sup&gt;&amp;#x2212;1} moduli set

Gbolagade, Kazeem Alagbe; Chaves, Ricardo; Sousa, Leonel; Cotofana, Sorin

doi:10.1109/iscas.2010.5537062

Cited by 14 publications

(3 citation statements)

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“…In terms of complexity, arithmetic operation in moduli 2 n +1 are more complex than moduli 2 n and 2 n -1. Therefore, 3n-bit dynamic range RNS moduli sets {2 n-1 -1, 2 n -1, 2 n } [34], {2 n -1, 2 n , 2 n+1 -1} [35] and {2 2n+1 -1, 2 n , 2 n-1 } [36] are reported by many researchers. The latest papers that consider reverse conversion using 3-moduli sets are [37][38][39][40].…”

Section: Introductionmentioning

confidence: 99%

Fast And Area-Efficient Reverse Converters For Five ModuliSet {2n+1, 2n-1-1, 2n, 2n+1-1, 2n-1}

Alvani

2024

EATP

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Introduction:This paper proposes two new reverse converters for balanced and wellformed five-moduli set {2 n +1, 2 n-1 -1, 2 n , 2 n+1 -1, 2 n -1}. The converters are planned in a twolevel architecture while appreciating adder base structures without utilizing any ROM, which results in an efficient implementation in VLSI circuits. Materials and Methods: To design both levels of the proposed reverse converters, Mixed-Radix Conversation (MRC) algorithm is employed. Results and Discussion: Unit gate delay and area estimation demonstrate the proposed reverse converter (DC1) is faster than other alternatives, the similar five moduli reverse converter, under distinctive dynamic ranges while the second design (DC2) requires less hardware cost. Conclusion:The synthesis results on Xilinx Virtex-7 FPGA illustrate that, comparing to the latest five moduli set reverse converters, the proposed converter (DC1) has achieved 11%, 12% and 11% improvement in speed for n = 12, 16 and 20, respectively.

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Section: Introductionmentioning

confidence: 99%

Fast And Area-Efficient Reverse Converters For Five ModuliSet {2n+1, 2n-1-1, 2n, 2n+1-1, 2n-1}

Alvani

2024

EATP

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“…The area and delay overheads are up to 35.6% and 45.2%, respectively. Therefore, previous studies have proposed several (2 n þ 1)-free moduli sets, such as f2 2n ; 2 n À 1; 2 nþ1 À 1g, f2 2n ; 2 n À 1; 2 nÀ1 À 1g [9], f2 n ; 2 n À 1; 2 2nÀ1 À 1g [10], and f2 n À 1; 2 n ; 2 2nþ1 À 1g [11], but they are fixed and difficult to implement in addressing the DR over-ratio problem.…”

Section: Introductionmentioning

confidence: 99%

“…Its function blocks were designed on the basis of Eqs. (7), (11), and (12). First, the operand preparation unit (OPU 1) is a bit organizer that simply performs permutations by using Eqs.…”

Section: Introductionmentioning

confidence: 99%

New adaptable three-moduli set {2n+k, 2n − 1, 2n−1 − 1} for residue number system-based finite impulse response implementation

Sheu

Siao

Hwang

et al. 2016

IEICE Electron. Express

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This paper presents a new adaptable three-moduli set, f2 n+k , 2 n − 1, 2 n−1 − 1g. It has three advantages for designing residue number system (RNS)-based digital signal processor (DSP) systems. First, it does not include a (2 n + 1)-type modulo, thus providing a high-speed and low-cost system design. Second, three parallel DSP module channels achieve more efficient delay-balancing, thereby enhancing the system operation speed. Third, the set possesses an adaptable 2 n+k modulo for avoiding over-ratio problems and reducing the system hardware overheads. Through the implementation of a mixed-radix conversion concept, an efficient converter was derived for the proposed adaptable moduli set. For system evaluation and comparison, the proposed adaptable and related moduli sets were used to implement a 16-tap RNS-based finite impulse response module that contains a forward converter, FIR module, and reverse converter. Based on TSMC 90-nm CMOS process technology, all implementations were synthesized to obtain layout results for a performance comparison. The design derived using the proposed moduli set achieved a 12%-46% AD 2 (area × delay 2 )saving compared with those derived using other moduli sets or binary number systems.

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A Hybrid Metaheuristic Algorithm for Features Dimensionality Reduction in Network Intrusion Detection System

Balogun¹,

Gbolagade²,

Arowolo³

et al. 2021

Computational Science and Its Applications – ICCSA 2021

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An improved RNS reverse converter for the {2<sup>2n+1</sup>−1, 2<sup>n</sup>, 2<sup>n</sup>−1} moduli set

Cited by 14 publications

References 7 publications

Fast And Area-Efficient Reverse Converters For Five ModuliSet {2n+1, 2n-1-1, 2n, 2n+1-1, 2n-1}

Fast And Area-Efficient Reverse Converters For Five ModuliSet {2n+1, 2n-1-1, 2n, 2n+1-1, 2n-1}

New adaptable three-moduli set {2<i><sup>n</sup></i><sup>+</sup><i><sup>k</sup></i>, 2<i><sup>n</sup></i> − 1, 2<i><sup>n</sup></i><sup>−1</sup> − 1} for residue number system-based finite impulse response implementation

A Hybrid Metaheuristic Algorithm for Features Dimensionality Reduction in Network Intrusion Detection System

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