An improved soft BCH decoder with one extra error compensation

Abstract

Abstract-In existing soft decision algorithms, a soft BCH decoders provides better error correcting performance but has much higher hardware complexity than a traditional hard BCH decoder. In this paper, a soft BCH decoder with both better error correcting performance and lower complexity is presented. The low complexity feature of the proposed architecture is achieved by dealing with least reliable bits. By compensating extra one error outside the least reliable set, the error correcting ability is improved. In addition, the proposed error locator evaluator evaluates error locations without Chien search, leading to high throughput. As compared with the traditional hard BCH decoder, the experimental result reveals that our proposed improved soft BCH decoder can achieve 0.75db coding gain for BCH (255,239) code. Implemented in standard CMOS 90nm technology, it can reach 316.3Mb/s throughput at 360MHz operation frequency with gate-count of 4.06K according to the post-layout simulations.

Improved High Code-Rate Soft BCH Decoder Architectures With One Extra Error Compensation

“…The proposed soft BCH decoder includes three major blocks: syndrome calculator, error-locator evaluator, and compensation error magnitude solver (CEMS) [11]. As compared with [9], the proposed soft BCH decoder enhances the error-correcting performance by compensating one extra error outside the least reliable locations while maintaining the low-complexity property.…”

“…As mentioned in Section II, the proposed soft decoder includes three major blocks. In [11], we discussed an efficient architecture for each block. However, in contrast to the CEMS presented in [11], the CEMS proposed in this brief will provide a new sharing architecture, leading to (t − 1)-multiplier hardware reduction.…”

“…In [11], we discussed an efficient architecture for each block. However, in contrast to the CEMS presented in [11], the CEMS proposed in this brief will provide a new sharing architecture, leading to (t − 1)-multiplier hardware reduction. The architecture comparison between the hard and soft BCH decoders is demonstrated in the end of this section.…”

Interpolation-based Chase BCH decoder

“…t = 8 for this code. With η = 4, the Chase decoder significantly outperforms both the generalized minimum-distance (GMD) decoder and the soft-decision decoder in [9], which assumes at most one error is not located in the 2t least reliable bits.…”

“…Despite the performance loss, its gate count is almost twice of the interpolation-based decoder. The soft-decision decoder in [9] has inferior performance and requires more logic gate than the interpolation-based decoder as well. More importantly, it needs to try 2 2t test vectors and the achievable throughput is 300 times lower.…”