An Improved VLSI Algorithm for an Efficient VLSI Implementation of a Type IV DCT That Allows an Efficient Incorporation of Hardware Security with a Low Overhead

Abstract

This paper aims to solve one of the most challenging problems in designing VLSI chips for common goods, namely an efficient incorporation of security techniques while maintaining high performances of the VLSI implementation with a reduced hardware complexity. In this case, it is very important to maintain high performance at a low hardware complexity and the overheads introduced by the security techniques should be as low as possible. This paper proposes an improved approach based on a new VLSI algorithm for including the obfuscation technique in the VLSI implementation of one important DSP algorithm used in multimedia applications. The proposed approach is based on a new VLSI algorithm that decomposes type IV DCT into six quasi-cycle convolutions and allows an efficient incorporation of the obfuscation technique. The proposed method uses a regular and modular structure called quasi-cyclic convolution and the obtained architecture is based on the architectural paradigm of systolic arrays. In this way we can obtain the advantages introduced by systolic arrays, especially high speed, with an efficient utilization of the hardware structure. Moreover, using the proposed VLSI algorithm, we can obtain the important benefit of attaining hardware security. Thus, a more efficient VLSI architecture for type IV DCT can be obtained, with a significant reduction of the hardware complexity, and an efficient incorporation of an improved hardware security mechanism with low overheads. These features are very important for resource-constrained common goods.

An Area-Efficient Unified VLSI Architecture for Type IV DCT/DST Having an Efficient Hardware Security with Low Overheads

“…As it can be seen from Section 2.1, we have designed a new VLSI algorithm for type IV DST that can be unified in a straightforward manner with a previous algorithm proposed by us in [29]. The obtained algorithm allows the decomposition of the computation of type IV DST using six computational structures that can operate in parallel.…”

“…The reference [29] is about a VLSI implementation of DCT IV. Since the VLSI algorithm for type IV DCT has been used with our proposed VLSI algorithm for DST IV for unification, it has similar performance as our unified VLSI architecture, while our solution computes both transforms using the same chip with a similar hardware complexity as that used for DCT IV presented in [29].…”

“…The architectures described in [26,28,29] have been developed to facilitate the incorporation of hardware security techniques.…”

“…Using the above VLSI algorithm for DST IV and a previous VLSI algorithm for DCT IV [29], we can obtain a unified VLSI algorithm for DCT/DST IV presented below.…”

“…There are very many good VLSI implementations for type II and type III DCT, and quite a few good hardware implementations for type IV DCT or type IV DST [20][21][22][23][24][25][26][27][28][29]. Among them, there are only a few unified solutions that can efficiently execute both transforms using a large portion of the area in common on the same chip [20][21][22]28].…”