An improvement and a fast DSP implementation of the bit flipping algorithms for low density parity check decoder

Abstract

<span lang="EN-US">For low density parity check (LDPC) decoding, hard-decision algorithms are sometimes more suitable than the soft-decision ones. Particularly in the high throughput and high speed applications. However, there exists a considerable gap in performances between these two classes of algorithms in favor of soft-decision algorithms. In order to reduce this gap, in this work we introduce two new improved versions of the hard-decision algorithms, the adaptative gradient descent bit-flipping (AGDBF) and adaptative reliability ratio weighted GDBF (ARRWGDBF). An adaptative weighting and correction factor is introduced in each case to improve the performances of the two algorithms allowing an important gain of bit error rate. As a second contribution of this work a real time implementation of the proposed solutions on a digital signal processors (DSP) is performed in order to optimize and improve the performance of these new approchs. The results of numerical simulations and DSP implementation reveal a faster convergence with a low processing time and a reduction in consumed memory resources when compared to soft-decision algorithms. For the irregular LDPC code, our approachs achieves gains of 0.25 and 0.15 dB respectively for the AGDBF and ARRWGDBF algorithms.</span>

Embedded Parallel Implementation of LDPC Decoder for Ultra-Reliable Low-Latency Communications

“…Te memory size requirement and the run time spent in the write/read memory accesses depend on the adopted data structure for both the H matrix and message storage. Te data structure used in previous works [10][11][12][13][14] is used in this run-time analysis. In this representation, the H matrix is represented as two separate two-dimensional arrays: the frst contains the column indexes of each matrix row, which is used for the horizontal processing, and the second contains the row indexes of each matrix column, which is used for the vertical processing.…”

“…end for line 7 Vertical processing (V2C computation) and LLR update: (11) for each variable node v j connected to c i (12) for every check node c a connected to v j (13) tmp � tmp + m c a ⟶ v j (14) end for line 12 (15) L(v j ) � L(0) v j + tmp (16) for every check node c a connected to v j (17) (18) end for line 16 (19) end for line 11 (20) end for line 3…”

“…Unlike the previous works [10][11][12][13][14], in this paper we propose an optimized version of the NMSA horizontal shufed scheduling algorithm by merging the horizontal and vertical steps into one step, thereby allowing to decrease the memory accesses and minimize the number of arithmetic operations.…”

“…Te frst part of the equation concerns the H matrix storage (Col table), and the second part concerns the messages storage (C2V[] and L(v j )). It is clear from equations ( 7) and ( 10) that the memory size required for the proposed data structure is lower by 50% than the data structure proposed in [10][11][12][13][14], and consequently, the run-time required for the memory access is highly reduced.…”

“…Several studies have recently focused on software implementations of LDPC decoders on multicore devices, using three soft implementation strategies for parallel processing: some works manipulate GPUs or x86 multicore to parallelize processing [10,11], others use SIMD architecture [12] to accelerate computation, and the third exploits multicore system on chip (SoC) to take advantage of hard acceleration and soft fexibility [13,14].…”