An In0.53Ga0.47As/In0.52Al0.48As/In0.53Ga0.47As double hetero-junction junctionless TFET

Hu, Linyong; Yang, Lin‐An; Zhang, Huawei; Zhang, Bingtao; Zhang, Wenting

doi:10.35848/1347-4065/ac0611

Cited by 3 publications

(2 citation statements)

References 40 publications

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“…For a better explanation, two kinds of tunneling are defined: 1) electrons in the valence band of the P + -type source region tunneling into the conduction band of SC is defined as SSTtunneling, and 2) electrons in the valence band of the P + -type source region tunneling into the conduction band of DSC is defined as SDT-tunneling. According to Equation ( 1) in [10], SST tunneling is far stronger than SDT tunneling in the off-and on-states. In the off-state, only SDTtunneling exists when L sc = 0 nm, but when L sc > 0 nm, SST-tunneling is also turned on and becomes stronger with the increase of L sc , both of which result in the change trend of I off .…”

Section: Influence Of Length Of Source-side Channel On Hdl-tfetmentioning

confidence: 99%

Design and Performance Optimization of InGaAs/InAlAs Dopingless Tunnel Field-effect Transistor

Liu,

Zhou,

et al. 2023

J. Phys.: Conf. Ser.

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In this work, an InGaAs/InAlAs dopingless tunnel field-effect transistor is designed and systematically examined through numerical simulations. In line with the charge plasma concept, the proposed device can not only create a p-n-i-n structure without doping to enhance electron tunneling but also effectively overcome issues caused by doping such as random doping fluctuation, high thermal budget, etc. By investigating the effects of the HfO2 length (L H), the source-side channel length (L sc), and the source-drain electrodes structure on the proposed device, it concludes that the best device characteristic can be acquired when L H is located between 110 nm and 128 nm, L sc=4 nm, and double source-drain electrodes are adopted.

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Section: Influence Of Length Of Source-side Channel On Hdl-tfetmentioning

confidence: 99%

Design and Performance Optimization of InGaAs/InAlAs Dopingless Tunnel Field-effect Transistor

Liu,

Zhou,

et al. 2023

J. Phys.: Conf. Ser.

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“…In the gate voltage amplification state, the presence of the depolarization field in the ferroelectric layer can not only increase the channel surface potential but also reduce the body factor of the device, effectively improving the I on and reducing the SS. To further improve the I on , the bulk material of FBHD-EHBTFET adopts the direct bandgap material In 0.53 Ga 0.47 As that has lower effective electron mass and band gap [27][28][29]. However, it is noted that ferroelectric materials will suffer from polarization fatigue, retention loss, and imprint effect under continuous operation, which may affect the device performance such as degrading I on and SS, weakening read-to-current ratio, lowering memory window, etc.…”

Section: Introductionmentioning

confidence: 99%

A symmetric heterogate dopingless electron-hole bilayer TFET with ferroelectric and barrier layers

Liu,

Zhou,

et al. 2024

Phys. Scr.

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In this paper, a symmetric heterogate dopingless electron–hole bilayer tunnel field-effect transistor with a ferroelectric layer and a dielectric barrier layer (FBHD-EHBTFET) is proposed. FBHD-EHBTFET can not only avoid random doping fluctuation and high thermal budget caused by doping, but also solve the issue that conventional EHBTFETs are unable to use the self-alignment process during device manufacturing. The simultaneous introduction of the symmetric heterogate and dielectric barrier layer can significantly suppress off-state current (I off). Ferroelectric material embedded in the gate dielectric layer can enhance electron tunneling, contributing to improving on-state current (I on) and steepening average subthreshold swing (SS avg). By optimizing various parameters related to the gate, ferroelectric layer, and dielectric barrier layer, FBHD-EHBTFET can obtain the I off of 1.11 × 10–18 A μm−1, SS avg of 12.5 mV/dec, and I on of 2.59 × 10–5 A μm−1. Compared with other symmetric dopingless EHBTFETs, FBHD-EHBTFET can maintain high I on while reducing its I off by up to thirteen orders of magnitude and SS avg by at least 51.2%. Moreover, investigation demonstrates that both interface fixed charge and interface trap can increase I off, degrading the off-state performance of device. The study on FBHD-EHBTFET-based dynamic random access memory shows that it has the high read-to-current ratio of 1.1 × 106, high sense margin of 0.42 μA μm−1, and long retention time greater than 100 ms, demonstrating that it has great potential in low-power applications.

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OFF-State Leakage Suppression in Vertical Electron–Hole Bilayer TFET Using Dual-Metal Left-Gate and N+-Pocket

Zhang

Wang

et al. 2022

Materials

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In this paper, an In0.53Ga0.47As electron–hole bilayer tunnel field-effect transistor (EHBTFET) with a dual-metal left-gate and an N+-pocket (DGNP-EHBTFET) is proposed and systematically studied by means of numerical simulation. Unlike traditional transverse EHBTFETs, the proposed DGNP-EHBTFET can improve device performance without sacrificing the chip density, and can simplify the manufacturing process. The introduction of the dual-metal left-gate and the N+-pocket can shift the point-tunneling junction and adjust the energy band and the electric field in it, aiming to substantially degrade the OFF-state current (IOFF) and maintain good ON-state performance. Moreover, the line tunneling governed by the tunneling-gate and the right-gate can further regulate and control IOFF. By optimizing various parameters related to the N+-pocket and the gate electrodes, DGNP-EHBTFET’s IOFF is reduced by at least four orders of magnitude, it has a 75.1% decreased average subthreshold swing compared with other EHBTFETs, and it can maintain a high ON-state current. This design greatly promotes the application potential of EHBTFETs.

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An In_0.53Ga_0.47As/In_0.52Al_0.48As/In_0.53Ga_0.47As double hetero-junction junctionless TFET

Cited by 3 publications

References 40 publications

Design and Performance Optimization of InGaAs/InAlAs Dopingless Tunnel Field-effect Transistor

Design and Performance Optimization of InGaAs/InAlAs Dopingless Tunnel Field-effect Transistor

A symmetric heterogate dopingless electron-hole bilayer TFET with ferroelectric and barrier layers

OFF-State Leakage Suppression in Vertical Electron–Hole Bilayer TFET Using Dual-Metal Left-Gate and N+-Pocket

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