An inductorless linear optical receiver for 20Gbaud/s (40Gb/s) PAM-4 modulation using 28nm CMOS

112 Gbit/s single-polarization silicon coherent receiver with hybrid-integrated BiCMOS linear TIA

“…The 2 channel TIA array pulls a total current of 128 mA (at the highest signal and LO power), yielding a low overall power consumption of 310mW or 2.8 mW/Gbit/s for 16-QAM transmission (and 5.8 mW for QPSK) in agreement with other work [7][8][9] .…”

Highly sensitive 10 Gb/s PAM‐4 optical receiver circuit for three‐dimensional optoelectronic integration

“…6 also plots the lines with 10 and 15 dB slopes (per decade), both originating at the point which represents our circuit's sensitivity. As can be observed, sensitivities of all PAM‐4 circuits are located above the 10 dB per decade line, and RXs from [10, 11] are the only ones below the line with the slope of 15 dB per decade of the bit‐rate increase. However, those values are estimated based on the reported post‐layout results.…”

“…References [10–14] report on PAM‐4 optical RXs. Circuits [10, 11] are designed for wire‐bonded PDs and their post‐layout simulation results are presented. They operate at 56 and 40 Gb/s, respectively.…”

Design and Performance Investigation of a New Distributed Amplifier Architecture for 40 and 100 Gb/s Optical Receivers

“…With the aid of Equ. 6b one can arrive to the following expression for the transconductance = (9) Investigating Equ. 9 reveals the following findings I.…”

“…However, for short-reach 100 Gb/s applications, solutions that use intensity modulation and direction detection are seen as more practical [8]. With the advances in semiconductor technologies, integrated circuits operating at 40 Gb/s have been realized in standard CMOS process [9]. Among all kinds of high speed circuits, the broadband amplifier is a key building block at both the transmitting and receiving ends, see Fig.…”