An Inexact Ultra-low Power Bio-signal Processing Architecture With Lightweight Error Recovery

Abstract

e energy e ciency of digital architectures is tightly linked to the voltage level (Vdd) at which they operate. Aggressive voltage scaling is therefore mandatory when ultra-low power processing is required. Nonetheless, the lowest admissible Vdd is o en bounded by reliability concerns, especially since static and dynamic non-idealities are exacerbated in the near-threshold region, imposing costly guard-bands to guarantee correctness under worst-case conditions. A striking alternative, explored in this paper, waives the requirement for unconditional correctness, undergoing more relaxed constraints. First, a er a run-time failure, processing correctly resumes at a later point in time. Second, failures induce a limited ality-of-Service (QoS) degradation. We focus our investigation on the practical scenario of embedded bio-signal analysis, a domain in which energy e ciency is key, while applications are inherently error-tolerant to a certain degree. Targeting a domain-speci c multi-core platform, we present a study of the impact of inexactness on application-visible errors. en, we introduce a novel methodology to manage them, which requires minimal hardware resources and a negligible energy overhead. Experimental evidence show that, by tolerating 900 errors/hour, the resulting inexact platform can achieve an e ciency increase of up to 24%, with a QoS degradation of less than 3%. Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for pro t or commercial advantage and that copies bear this notice and the full citation on the rst page. Copyrights for components of this work owned by others than the author(s) must be honored. Abstracting with credit is permi ed. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior speci c permission and/or a fee. Request permissions from permissions@acm.org. INTRODUCTIONe emergence of embedded devices, able to continuously acquire and wirelessly transmit the sensed data, is fostering a revolution across the IT landscape [3], opening novel and exciting opportunities in many elds, ranging from environmental protection [30] to domotics [16].Among them, healthcare applications are of particular interest, especially the ones related to monitoring chronic cardiovascular disorders [1]. In this scenario, sensor appliances (named Wireless Body Sensor Nodes, WBSNs) enable the long-term acquisition of bio-signals, outside of a hospital environment and with minimal medical supervision [18].E ciency is key for WBSNs, as the saved energy translates both in smaller form factors (by requiring smaller ba eries) and longer autonomies. Herein, we focus our investigation on the energy optimization of the Digital Signal Processing (DSP) applications executing on WBSNs. Such routines analyze acquisitions, deriving compact feature sets, which are then transmi ed on the wireless link [7]. ey must be supported within a tight energy envelope, because...

Online Obstructive Sleep Apnea Detection on Medical Wearable Sensors

“…Given that an autonomous device with online analysis has a longer battery life than when streaming the sampled data to a remote device such as a smartphone, provided that the embedded computations required for signal processing and classification are lightweight enough, which has been proven by the works of Rincón et al, Crepaldi et al,and Basu et al [54]- [57]. Thus, we need to carefully select the features we use for the OSA classification.…”

A Formal Framework for Maximum Error Estimation in Approximate Logic Synthesis

“…While approximation can be exploited at various levels of the hardware/software stack [1], [8], circuit-level AC methodologies are most related to our contribution. In particular, we focus on Approximate Logic Synthesis, which consists of manipulating the Boolean function implemented by a circuit to obtain an inexact counterpart, as opposed to Voltage Overscaling, where the voltage supply of an architecture is altered, injecting timing errors [9], [10]. Some notable efforts in inexact circuit research focus on manually designing specific arithmetic units, such as adders [11] or multipliers [12], [13], while others adopt a more generic approach, enabling the simplification of any combinatorial circuit [2], [3], [4], [7], [14], [15], [16].…”

Heterogeneous and Inexact: Maximizing Power Efficiency of Edge Computing Sensors for Health Monitoring Applications

“…Multi-core system As depicted in Fig. 2, and similarly to [2] and [12], the target platform features multiple RISC processors, which are interconnected through combinational crossbars to separate data and instruction memory banks. Each processor implements a Harvard architecture [13], supported by a three-stage pipeline, which can be clock-gated by a synchronizer unit while waiting for another processor to finish its task or when a kernel acceleration is running on the CGRA.…”

“…Similarly to [12], we classify the transient errors (i.e., bitflips induced by voltage droops) affecting the execution of the system or the computed results into three categories:…”