An InGaSb p-channel FinFET

Abstract

We demonstrate the first InGaSb p-channel FinFET. Towards this goal, we have developed a fin dry-etch technology which yields fins as narrow as 15 nm with vertical sidewalls, an aspect ratio greater than 10 and low sidewall interface state density. We have also realized Si-compatible ohmic contacts with ultra-low contact resistivity of 3.5·10 -8 ·cm 2 . InGaSb FinFETs with fin widths down to 30 nm and gate lengths down to 100 nm have been fabricated. The Al 2 O 3 gate oxide has an EOT of 1.8 nm. A high g m of 122 S/ m is obtained in devices of W f = 100 nm and L g = 100 nm. In the smallest devices with W f = 30 nm and L g = 100 nm, a g m of 78 S/ m is achieved.

Epitaxial growth of GaSb and InAs fins on 300 mm Si (001) by aspect ratio trapping

“…In particular, GaSb/InAs broken gap heterojunction Tunnel Field-Effect Transistors (TFET) with record high-ON current have recently been demonstrated [4]. Moreover, InAs and GaSb are thought to be promising candidates to replace Si in sub-7 nm Complementary Metal-Oxide-Semiconductor (CMOS) devices due to their respective high electron and hole mobilities [5][6][7][8]. In addition to low voltage operation transistors, 6.1 Å family compound semiconductors are of great interest for near-and mid-infrared optoelectronic devices [9,10], and are considered very attractive for the fabrication of several building blocks required to develop silicon photonic platforms.…”

Improved Electrostatics through Digital Etch Schemes in Vertical GaSb Nanowire p-MOSFETs on Si

“…6−8 However, the main challenge of a Sb-based MOSFET to completely benefit from the high mobility of the bulk material is the poor electrostatics originating from the high level of interface and border traps. To substantially improve the electrostatic control for scaled transistors, various nanowire-based multigate architectures such as FinFETs 9 and vertical gate-all-around (GAA) MOSFETs 10,11 are being pursued. A key step to achieve scaled nanowire diameters or fin widths for III−V semiconductors has been to employ digital etch (DE) methods to both reduce dimensions and provide native oxide removal.…”

Temperature characteristics of FinFET based on channel fin width and working voltage

“…Many new field effect transistor (FET) structures have been extensively explored given that the metal oxide semiconductor FET (MOSFET) technology has continued to approach its downscaling limits. One of the relatively newer FETs is the FinFET as shown in Figure 1 [6], a transistor-structured FET that is a popular research topic in the academic field and semiconductor industry [7][8][9]. The one new promising MOSFET architecture is the FinFET see Figure 1 that have the gate surrounding the channel which gives a better control and therefore reduces current leaking, one way of creating a FinFET is to use a nanowire as a channel and build a gate around it.…”