2007
DOI: 10.1093/ietfec/e90-a.10.2108
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An Inhibitory Neural-Network Circuit Exhibiting Noise Shaping with Subthreshold MOS Neuron Circuits

Abstract: We designed subthreshold analog MOS circuits implementing an inhibitory network model that performs noise-shaping pulsedensity modulation (PDM) with noisy neural elements, with the aim of developing a possible ultralow-power one-bit analog-to-digital converter. The static and dynamic noises given to the proposed circuits were obtained from device mismatches of current sources (transistors) and externally applied random spike currents, respectively. Through circuit simulations we confirmed that the circuit exhi… Show more

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Cited by 10 publications
(7 citation statements)
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“…Phase synchronization among isolated circuits/PLL (CMOS) [48] Synaptic depression [49] Static Burst signal detection (SET) [50] Noise shaping in inhibitory neural networks [51] Dynamic/static Noise shaping AD conversion (CMOS [52], SET [53]) manufacturing methods, such as those based on molecular self-assembly. Second, regularity also facilitates reuse of logic designs.…”
Section: Cellular Automata Architecturesmentioning
confidence: 99%
“…Phase synchronization among isolated circuits/PLL (CMOS) [48] Synaptic depression [49] Static Burst signal detection (SET) [50] Noise shaping in inhibitory neural networks [51] Dynamic/static Noise shaping AD conversion (CMOS [52], SET [53]) manufacturing methods, such as those based on molecular self-assembly. Second, regularity also facilitates reuse of logic designs.…”
Section: Cellular Automata Architecturesmentioning
confidence: 99%
“…CIRCUIT IMPLEMENTATION Fig. 3 shows the model of the proposed circuit, consisting of three neuronal elements, the minimum number of units required to achieve a considerable signal-to-noise ratio ( [12]). The neurons receive the same analog input through excitatory synapses (•) and produce digital pulses toward the global inhibitor Σ [19].…”
Section: Single-electron Integrate and Fire Neuronmentioning
confidence: 99%
“…A number of neuromorphic circuits that operate by utilizing noises and device fabrication mismatches have been proposed. They include neuromorphic CMOS circuits utilizing device fabrication mismatches and environmental noises [12], single-electron circuits employing thermally induced stochastic resonance (SR) (see [13] for details on SR) in signal transmission [14], and single-electron networks performing synchrony detection [15]. This paper explores the possibility of creating novel circuit architectures with single-electron devices, by employing environmental (dynamic) noises, and static noises originating from fabrication mismatches.…”
Section: Introductionmentioning
confidence: 99%
“…On the other hand, many biological systems process information with the help of external or thermal noises, for example, see [2][3][4][5][6][7][8][9][10]. To reproduce this behavior, circuits that exploit noises efficiently, instead of removing them, have been proposed [11][12][13][14][15][16][17].…”
Section: Introductionmentioning
confidence: 99%