An Innovative I/O Budgeting Methodology for Hierarchical SoC Development

Meher, Manas Ranjan; Ullmann, Wolfgang

doi:10.1109/isocc47750.2019.9027653

Cited by 1 publication

(1 citation statement)

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“…Fig. 1 (a) shows an example of a SoC module including various building blocks integrated inside a single chip [7]- [9]. SiP systems are very dense devices combining separate chips implemented in different process and packaged together using a two-dimensional (2-D) or three-dimensional (3-D) substrate, as depicted in Fig.…”

Section: Introductionmentioning

confidence: 99%

A Reconfigurable Single-Supply Multiple-Level Down-Shifter for System-on-Chip Applications

Karimi

Ali

Hassan

et al. 2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

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A novel level down shifter intended for translation of signals with different amplitudes in System-on-Chip (SoC) applications is presented. This new single supply down-shifter architecture, implemented in a 0.35-µm AMS CMOS technology provides multiple reconfigurable levels. A diode connected circuit structure, a current source, five transmission gates, a diodesupercapacitor combination, and input/output buffers are employed to implement this reconfigurable level shifter. The circuit receives a pulse shaped signal with an amplitude of 3.3 V, and provides three different signals with nominal amplitudes of 1.2 V, 1.8 V, and 2.5 V depends on the circuit configuration. The proposed circuit successfully drives a range of capacitive loads between 10 fF and 350 pF. The presented circuit consumes a static and a dynamic power consumptions of 62.37 pW and 108.9μW, respectively from a 3.3V supply, at an operating frequency of 1 MHz and a capacitive load of 10 pF. Post-layout simulation results show that the fall and rise propagation delays of the three configurations are in the range of 0.54 ns-26.5 ns and 11.2 ns-117.2 ns, respectively. It occupies an area of 80 µm×100 µm.

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Section: Introductionmentioning

confidence: 99%