An input signal dependent 8-to-12 bit variable resolution SAR ADC with digitally implemented bit enhancement Logic

An artificial intelligence‐based 4‐to‐10‐bit variable resolution Flash ADC with 3.6 to 1.04 GS/s sampling rate

“…to vary the resolution of Flash ADC. For this purpose, a simple 4-bit Flash ADC has been designed, and with the help of AI (to predict the bits), its resolution is enhanced from 4 to 10 bits without much increasing the design complexity, area, and power, unlike the work done in Kandpal et al 31 for SAR ADC where resolution is enhanced from 8 to 12 bits without any prediction logic. Starting with a simple 4-bit Flash ADC also helped in designing a clocked comparator with relaxed offset, power, and low area as compared to that used in 8-bit SAR ADC in work.…”

“…Starting with a simple 4-bit Flash ADC also helped in designing a clocked comparator with relaxed offset, power, and low area as compared to that used in 8-bit SAR ADC in work. 31 To make the proposed ADC input signal dependent and artificially intelligent with the variable resolution, it is first required to make the relation between ADC output D out and sampled analog input V in . This is accomplished by first converting D out to an analog value V DAC using a 5-bit DAC, and the difference between V DAC and V in is then converted into a 2-bit digital output S 3 and S 2 by implementing a two-bit voltage-to-digital converter 32 that is made up of a V to T and then T to D. Therefore, S 3 and S 2 bits are generated automatically after finding the best-fit resolution for a given input voltage.…”

“…The speed of high-resolution Flash ADC degrades when moving from 4 to 10 bits. Hence, the execution time of sorting algorithm and speed of comparator play an important role in designing the higher resolution high-speed Flash ADC, unlike the work in Kandpal et al 31 where the speed of ADC is relatively low. The time complexities of different algorithm are analyzed in this work as the asymptotic behavior of an algorithm directly impacts the speed of Flash ADC to ensure less degradation in sampling rate of overall Flash ADC.…”

“…Once the REL block generates the additional bit, there is a chance that the digital bits in D f inal (from Step 3 in Section 3.1.1) are incorrect due to the fluctuations in process, voltage, and temperature (PVT) or coupling uncertainties and so on. Unlike in Kandpal et al, 31 prediction block is introduced here to predict the extra bits of Flash ADC and tackles the PVT related issues of REL bits. The working of this block is explained below.…”