An input test pattern for characterization of a full-adder and n-bit ripple carry adder

Mewada, Manan; Zaveri, Mazad

doi:10.1109/icacci.2016.7732055

Cited by 8 publications

(2 citation statements)

References 4 publications

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“…On the other hand, the propagation delay of a FA is dependent on the previous input combination (A, B, C in ) and the current input combination (A, B, C in ). Hence, the power dissipation and critical path delay is measured for all possible 48 transitions, presented in [17]. The Power-Delay product (PDP) (measured in f J), Area-Power Product (APP) and the Area-Delay product (ADP) are calculated while considering each transistor as unit area.…”

Section: A Performance Of Fa As Single Cellmentioning

confidence: 99%

Energy Efficient Full Swing GDI Based Adder Architecture for Arithmetic Applications

Aggarwal,

Garg

2024

Wireless Pers Commun

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Adders are one of the most important digital components used in any arithmetic applications. Many improvements in past have been made to improve its architecture. In this paper, we present two new symmetric designs for Energy efficient full adder cells featuring GDI (Gate-Diffusion Input) logic. The main design objectives for these adder modules are to operate at Low-Power with reduced area but also provide full-voltage swing. In the first (AEG-FA) design, a new approach of Inverted and Non-Inverted Carry-ins were taken to give complementary Carry-out and Sum with desired performance. These were then applied in different combinations to form higher bit width Adder architecture. This provides a higher degree of design freedom to target a wide range of applications, hence reducing design efforts. The second (PEG-FA) design is based on conventional approach which tries to reduce the critical path delay and lower switching activity in GDI circuit, providing Low-Power and high speed digital component at full voltage swing circuit. Many of the previously reported adders in literature suffered from the problems of lowswing and high noise when operated at low supply voltages. These two new designs successfully operate at low voltage with high signal integrity and driving capability. In order to evaluate the performance of proposed full adders, we incorporated 8-bit ripple carry adders. The studied circuits are optimized for energy efficiency using 45 nm CMOS process technology. The comparison between these novel circuits with standard full adder cells shows improvement in terms of Area, Delay, Power and Power-Delay-Product (PDP), Area-Delay Product (ADP), Area-Power Product (APP). At architecture level proposed adder shows 12.8% over CMOS, 14.8% over hybrid and 11.4% over other GDI logic power savings, by having almost 55% reduction in area.

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Section: A Performance Of Fa As Single Cellmentioning

confidence: 99%

Energy Efficient Full Swing GDI Based Adder Architecture for Arithmetic Applications

Aggarwal,

Garg

2024

Wireless Pers Commun

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“…The most critical element of the test is regarded as the carry'. A hybrid circuit that extends the spread of two bits is known as a half-adder, while one that extends the spread of three bits is known as a full-adder [18].…”

Section: Literature Reviewmentioning

confidence: 99%

Internet of Things Based Reconfigurable SIMD Processor for High-Speed End Devices in FPGA

2023

Teh. vjesn.

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This research article proposed the reconfigurable Single Instruction Multi Data (SIMD) processor design to speed up the accelerated computing task in IoT operations. Single Instruction Multi Data models leverage the parallel real source to speed up computing accelerated tasks. It proposes the utilization of reconfigurable Kogge Stone-dependent hybrid adder structures, now referred to as KS-CPA, in which reconfiguration occurs during the addition operation. The Least Significant Bits (LSB) are processed using a carry propagate adder, while the Most Significant Bits (MSB) are computed using the Kogge Stone adder. Depending on the data width and deviceaccessible energy resources, the hybrid configuration of the adder offers the 4-bit, 8-bit, and 16-bit addition. The adder form is identified by a shift in the configuration of its Carry Look-ahead and then by a Kogge Stone Adder (KSA). Throughout the activity, the KS-CLA crossbreed configuration is used to attain the fastest speed and low energy usage. The effectiveness, including its proposed hybrid adder, is evaluated by looking at the speed, energy, and area parameters, including a suitable area use during rapid applications in which both less delay and low power adders are required. Considering these, we are structuring an IoT processor that can be reconfigured to gain from SIMD. We have demonstrated that our hybrid adder-enhanced processor saves energy up to 13% and reduces 27% latency. The proposed 16 and 32-bit adders will boost time, power, and Area Delay Product (ADP) by almost 18-24% and 13-19% respectively.

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Estimating the Maximum Propagation Delay of 4-bit Ripple Carry Adder Using Reduced Input Transitions

Mewada

Zaveri

Lakhlani

2017

Communications in Computer and Information Science

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An input test pattern for characterization of a full-adder and n-bit ripple carry adder

Cited by 8 publications

References 4 publications

Energy Efficient Full Swing GDI Based Adder Architecture for Arithmetic Applications

Energy Efficient Full Swing GDI Based Adder Architecture for Arithmetic Applications

Internet of Things Based Reconfigurable SIMD Processor for High-Speed End Devices in FPGA

Estimating the Maximum Propagation Delay of 4-bit Ripple Carry Adder Using Reduced Input Transitions

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