An Instruction Issuing Approach to Enhancing Performance in Multiple Functional Unit Processors

Acosta,; Kjelstrup,; Torng,

doi:10.1109/tc.1986.1676841

Cited by 85 publications

(7 citation statements)

References 18 publications

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“…The scalar instructions in Jetpipeline are designed based on RISC, and it is easy to apply the parallelization. Since Jetpipeline can execute up to four scalar instructions independently of the operation type, it is expected that the dispatch stack method [11] used in the superscalar processor is suited.…”

Section: Parallelization Instruction Scheduling For Scalar Instructionmentioning

confidence: 99%

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A scheduling method for instruction-level parallel processing of vector and scalar instructions

et al. 1999

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Section: Parallelization Instruction Scheduling For Scalar Instructionmentioning

confidence: 99%

“…Then it is possible to realize the parallel execution of the scalar instructions using the parallelization algorithm, such as dispatch stack method [11]. It should also be noted that the vector instructions are generated before the parallelization in Jetpipeline.…”

Section: Introductionmentioning

confidence: 99%

A scheduling method for instruction-level parallel processing of vector and scalar instructions

et al. 1999

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“…This line of investigation into the logic needed to perform multiple-issue was continued by various researchers [72,73,[77][78][79][80][81]. This idea, of multiple instruction issue of sequential programs, was probably first referred to as superscalar execution by Agerwala and Cocke [82].…”

Section: Hardware Features To Support Ilp Executionmentioning

confidence: 99%

Instruction-Level Parallel Processing: History, Overview, and Perspective

Rau

Fisher

1993

Instruction-Level Parallelism

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instruction-level parallelism, VLIW processors, superscalar processors, pipelining, multiple operation issue, speculative execution, scheduling, register allocation Instruction-level Parallelism CILP) is a family of processor and compiler design techniques that speed up execution by causing individual machine operations to execute in parallel. Although ILP has appeared in the highest performance uniprocessors for the past 30 years, the 1980s saw it become a much more significant force in computer design. Several systems were built, and sold commercially, which pushed ILP far beyond where it had been before, both in terms of the amount of ILP offered and in the central role ILP played in the design of the system. By the end of the decade, advanced microprocessor design at all major CPU manufacturers had incorporated ILP, and new techniques for ILP have become a popular topic at academic conferences. This article provides an overview and historical perspective of the field of ILP and its development over the past three decades.

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“…Unter idealen Bedingungen kann ein Befehlsstrom somit viermal so schnell bearbeiten werden,wie von einem entsprechenden skalaren Prozessor (Speedup 4). Tatsächlich wird dieser Wert in der Realität jedoch nur selten erreicht,da in den meisten Programmen Abhängigkeiten existieren,die die parallele Verarbeitung der Befehle behindern.Von Acosta,Kjelstrup und Torng[11,6] wurde der Speedup,der durch die superskalare Arbeitsweise erzielt wird,mit unterschiedlichen,jeweils simulierten theoretischen Prozessoren untersucht,wobei jeweils der wissenschaftliche Benchmark Livermore Loop verwendet wurde. Im besten Fall wurde hierbei ein Wert von 2,79 gemessen.…”

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Superskalare Prozessoren

Menge¹

1998

Informatik-Spektrum

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Zusammenfassung Als superskalar wird ein Prozessor bezeichnet, der ein sequentiell geschriebenes Programm zur Laufzeit parallelisiert und pro Takt im Durchschnitt mehr als einen Befehl ausführt. Die Spanne der superskalaren Prozessoren reicht dabei von solchen, die nur aufeinanderfolgende Befehle parallelisieren können, wie z.B. dem Pentium, bis zu solchen, die die Befehle umordnen und in einer vom Programm abweichenden Reihenfolge ausführen können, wie z.B. dem Pentium II oder dem PowerPC 604. Die dabei verwendeten Mechanismen und Algorithmen werden in diesem Beitrag beschrieben.Summary A superscalar processor executes a pure sequential instruction stream in a parallel manner. The parallelization is carried out on the fly while a program is in execution. There are many techniques to realize such a processor.A simple way is to execute in parallel only immediatly adjacent instructions just in the order they are placed in the program.A much complex but more efficient way is to reorder the original instructions and execute them in a new arrangement. This paper descripes methods and techniques realized in superscalar processors.

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An Instruction Issuing Approach to Enhancing Performance in Multiple Functional Unit Processors

Cited by 85 publications

References 18 publications

A scheduling method for instruction-level parallel processing of vector and scalar instructions

A scheduling method for instruction-level parallel processing of vector and scalar instructions

Instruction-Level Parallel Processing: History, Overview, and Perspective

Superskalare Prozessoren

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