An instruction throughput model of superscalar processors

ACM Trans. Archit. Code Optim.

Eeckhout

2015

Superscalar in-order processors form an interesting alternative to out-of-order processors because of their energy efficiency and lower design complexity. However, despite the reduced design complexity, it is nontrivial to get performance estimates or insight in the application-microarchitecture interaction without running slow, detailed cycle-level simulations, because performance highly depends on the order of instructions within the application's dynamic instruction stream, as in-order processors stall on interinstruction dependences and functional unit contention. To limit the number of detailed cycle-level simulations needed during design space exploration, we propose a mechanistic analytical performance model that is built from understanding the internal mechanisms of the processor.The mechanistic performance model for superscalar in-order processors is shown to be accurate with an average performance prediction error of 3.2% compared to detailed cycle-accurate simulation using gem5. We also validate the model against hardware, using the ARM Cortex-A8 processor and show that it is accurate within 10% on average. We further demonstrate the usefulness of the model through three case studies:(1) design space exploration, identifying the optimum number of functional units for achieving a given performance target; (2) program-machine interactions, providing insight into microarchitecture bottlenecks; and (3) -We added modeling of an arbitrary number of functional units of any type in contrast to a fixed number in the ISPASS paper (i.e., 4 ALUs and 1 unit for all other types). -We completely revised the modeling of interinstruction dependences and unified it with the functional unit contention modeling. -We added modeling of memory-level parallelism, which has a nonnegligible impact on performance for some benchmarks that were not evaluated in the ISPASS paper. -We validated the model against hardware.-We added a case study on sizing the number of functional units. -We reevaluated all other case studies using the new model and revealed new insights about the interaction between dependences and functional unit contention.Permission to make digital or hard copies of part or all of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies show this notice on the first page or initial screen of a display along with the full citation. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, to republish, to post on servers, to redistribute to lists, or to use any component of this work in other works requires prior specific permission and/or a fee.

Section: Analytical Modelingmentioning

confidence: 99%

“…Most of the previous work on functional unit contention has focused on out-of-order processors, such as Taha and Wills [2008]. Other work, such as Noonburg and Shen [1994], Lee [2010], and Zhu et al [2005] has models that can be applied for in-order processors as well.…”

Section: Interinstruction Dependence Modeling and Functional Unit Conmentioning

confidence: 99%

Mechanistic Analytical Modeling of Superscalar In-Order Processor Performance

Breughe

ACM Trans. Archit. Code Optim.

Eeckhout

2015

“…Karkhanis and Smith [17] extend this simple mechanistic model to build a complete performance model that assumes sustained steady-state issue performance punctuated by miss events. Taha and Wills [28] propose a mechanistic model that breaks up the execution into so-called macro blocks, separated by miss events. Eyerman et al [8] propose the interval model for superscalar out-of-order processors.…”

Section: Analytical Modelingmentioning

confidence: 99%

A mechanistic performance model for superscalar in-order processors

Breughe

2012 IEEE International Symposium on Performance Analysis of Systems &Amp; Software

Eeckhout

2012

Mechanistic processor performance modeling builds an analytical model from understanding the underlying mechanisms in the processor and provides fundamental insight in program-microarchitecture interactions, as well as microarchitecture structure scaling trends and interactions. Whereas prior work in mechanistic performance modeling focused on superscalar out-of-order processors, this paper presents a mechanistic performance model for superscalar in-order processors. We find mechanistic modeling for inorder processors to be more challenging compared to outof-order processors because the latter are designed to hide latencies, and hence from a modeling perspective, detailed modeling of instruction execution latencies and dependencies is not required.The proposed mechanistic performance model for superscalar in-order processors models the impact of non-unit instruction execution latencies, inter-instruction dependencies, cache/TLB misses and branch mispredictions, and achieves an average performance prediction error of 2.5% compared to detailed cycle-accurate simulation. We extensively evaluate the model's accuracy and we demonstrate its usefulness through three applications: (i) we compare inorder versus out-of-order performance, (ii) we quantify the impact of compiler optimizations on in-order performance, and (iii) we perform a power/performance design space exploration.

“…Our toolbox today consists of a number of options. One methodology-analytical modeling [Karkhanis and Smith 2004;Taha and Wills 2008]-uses a fast, high-level approach to understanding application performance. Interval modeling [Eyerman et al 2009] is an example of an analytical, mechanistic model that can quickly and reliably predict the performance of single-threaded workloads on modern machines.…”

Section: Introductionmentioning

confidence: 99%

An Evaluation of High-Level Mechanistic Core Models

Carlson

Heirman²,

ACM Trans. Archit. Code Optim.

et al. 2014

280

136

Large core counts and complex cache hierarchies are increasing the burden placed on commonly used simulation and modeling techniques. Although analytical models provide fast results, they do not apply to complex, many-core shared-memory systems. In contrast, detailed cycle-level simulation can be accurate but also tends to be slow, which limits the number of configurations that can be evaluated. A middle ground is needed that provides for fast simulation of complex many-core processors while still providing accurate results.In this article, we explore, analyze, and compare the accuracy and simulation speed of high-abstraction core models as a potential solution to slow cycle-level simulation. We describe a number of enhancements to interval simulation to improve its accuracy while maintaining simulation speed. In addition, we introduce the instruction-window centric (IW-centric) core model, a new mechanistic core model that bridges the gap between interval simulation and cycle-accurate simulation by enabling high-speed simulations with higher levels of detail. We also show that using accurate core models like these are important for memory subsystem studies, and that simple, naive models, like a one-IPC core model, can lead to misleading and incorrect results and conclusions in practical design studies. Validation against real hardware shows good accuracy, with an average single-core error of 11.1% and a maximum of 18.8% for the IW-centric model with a 1.5× slowdown compared to interval simulation.