An integer programming method for constructing tightly coupled VLSI subarrays

Qian, Junyan; Zhou, Zhide; Zhao, Liang; Gu, Tao; Chang, Liang

doi:10.1587/elex.13.20160359

Cited by 3 publications

(2 citation statements)

References 10 publications

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“…An efficient algorithm based on the A‐star algorithm for accelerating the reconfiguration of power‐efficient VLSI processor subarrays that meet the real‐time constraints and lower power consumption of the embedded systems was proposed in Ref. . Then an algorithm (denoted as Csat in this paper) based on satisfiability was proposed in Ref.…”

Section: Introductionmentioning

confidence: 99%

An efficient method for reconfiguring power‐efficient VLSI array with maximum satisfiability

Qian

Chen

Zhao

et al. 2018

IEEJ Transactions Elec Engng

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Techniques to determine subarrays when processing elements (PEs) of very large scale integration (VLSI) arrays become faulty have been investigated extensively. In this paper, we propose a maximum satisfiability (MaxSAT)-based method for the reconfiguration of a two-dimensional degradable VLSI array with faulty PEs. A MaxSAT model is developed such that the target array can be constructed utilizing the efficient MaxSAT solver. Using the proposed method, we are able to find a maximum logical array with the least number of long interconnects and minimizing the number of the long interconnects that will lead to less rerouting costs. Experimental results show that the proposed method is able to reduce most redundant interconnects for the host array compared to earlier works.

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Section: Introductionmentioning

confidence: 99%

An efficient method for reconfiguring power‐efficient VLSI array with maximum satisfiability

Qian

Chen

Zhao

et al. 2018

IEEJ Transactions Elec Engng

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“…Therefore, a divide-and-conquer algorithm (denoted as CMTA in this paper) was proposed for a tightly-coupled MTA in [12], resulting in significant improvements over DPGCR in terms of the total inter-length. Qian et al [13] proposed a method based on integer programming for constructing tightly-coupled subarrays. However, neither DPGCR nor CMTA guarantees the resultant logical mesh array on the number of the long-interconnects is optimal.…”

Section: Introductionmentioning

confidence: 99%

Satisfiability-based method for reconfiguring power efficient VLSI array

Qian

Cao

et al. 2016

IEICE Electron. Express

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Fault-tolerant techniques are absolutely vital for large scale multiprocessor array as it suffers from frequent hardware defects or soft faults. This paper presents a satisfiability (SAT)-Based method for the reconfiguration of a two-dimensional degradable very-large-scale integration (VLSI) array with faulty processing elements (PEs). An SAT model of the target array is proposed such that the target array can be constructed by using the efficient SAT solver. For minimizing the interconnection length of the target array, we present an incomplete algorithm, to search a target array with suitable interconnection length to meet the system requirement. Our evaluations show that the proposed incomplete algorithm is efficient, which is compared with the state-of-the-art.

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