An Integrated Approach and Tool Support for the Design of FPGA-Based Multi-Grain Reconfigurable Systems

Abstract

Dynamic partial reconfiguration technique can be used to modify regions of an FPGA as large as the whole reconfigurable fabric or as small as individual logic elements. However, FPGA manufacturers have focused their efforts on designing tools that support the design of monolithic reconfigurable accelerators spanning large regions of the device. Nevertheless, in some applications, it is enough to fine-tune the accelerators' behavior instead of changing them entirely. In these cases, rather than allocating new accelerators, it is possible to reconfigure individual logic elements of the circuit, such as look-up tables or flip-flops. There is also an intermediate approach that targets the reconfigurability of accelerators composed of several tightly interconnected modules, such as overlays. In those architectures, it is possible to reconfigure only the modules that differ between the existing accelerator versions, thus reducing the reconfigurable footprint granularity. This paper proposes a classification of the approaches above, categorizing them as coarse, fine, and medium grain, respectively. There are neither commercial nor academic tools supporting multi-grain reconfiguration to take advantage of each granularity strength on commercial FPGAs. Differently, this paper proposes a tool called IMPRESS, that provides design-time and run-time support for multi-grain reconfiguration in Xilinx 7 Series FPGAs. Specific criteria are provided to combine the different granularity levels, trading off the benefits in terms of flexibility and performance, with different design and run-time costs. Two use cases in the image processing and neural network domains have been implemented to show how IMPRESS can build multi-grain reconfigurable systems.

Mapping Processing Elements of Custom Virtual CGRAs onto Reconfigurable Partitions

“…Due to the lack of mature, commonly available physical CGRA architectures and both enormous costs and extremely long development of custom ASIC CGRA, virtual architectures implemented as overlays atop FPGAs are not uncommon [4][5][6][7][8][9][10][11][12][13][14][15]. Apart from serving prototyping purposes for architecture development, Virtual Coarse-Grained Reconfigurable Architectures (VCGRAs) can be used to provide a convenient high abstraction layer for FPGA-based systems end users.…”

“…Multiple architectures, analysis, techniques, and tools for Virtual CGRAs have been introduced over the years [4][5][6][7][8][9][10][11][12][13][14][15]21]. In spite of the lack of standardization, different motivations and approaches to virtual CGRA architecture design, common features, and solutions can be observed.…”

“…Most commonly, VCGRAs are used with general-purpose CPUs, not only as external hosts controllers but often in the form of soft cores implemented in FPGA [7] or processors embedded with FPGA in a SoC [6,22]. Moreover, as the granularity is defined by the abstract programming model, fine-grained logic can be used alongside it to provide better adaptability and state machine logic handling in a so-called Mixed-Grained or Multi-Grained approach [15,20,25].…”

“…Recently introduced IMPRESS [14,15] is an academic design flow for Xilinx FPGAs capable of mapping virtual architectures onto networks of reconfigurable partitions. The tool is based on set of TCL scripts working under Xilinx Vivado.…”

Agile FPGA Computing at the 5G Edge: Joint Management of Accelerated and Software Functions for Open Radio Access Technologies

“…The run-time spatial-temporal exploitation of FPGA compute resources requires certain applications to fulfill some strict latency requirements in order not to suffer service downtimes. Different works tried to improve the PR latency and reconfiguration control overheads [9][10][11]. Another major setback for more widespread use of the PR methods is concerns related to data privacy and security when FPGA devices are used as shared computing resources in multi-tenant edge or cloud applications.…”