An integrated differential 60 GHz sliding-IF receiver in SiGe BiCMOS

Abstract

This paper presents an integrated 60 GHz sliding-IF receiver fabricated in a 0.25 ȝm SiGe BiCMOS technology. The receiver chain consists of a front-end and an IF IQ demodulator centered at around 12 GHz. A 48 GHz PLL is used to generate the front-end LO signal and the IF quadrature LO signals. The measured LNA noise figure is around 6.6 dB. Digital words are used to control the VGA gains and IQ mismatches through a Serial Peripheral Interface (SPI) to reduce the number of bond pads. The receiver chip has been mounted onto an application board, where an on-board Vivaldi antenna has already been fabricated. An overall conversion gain of 81 dB has been measured with tuning range larger than 30 dB. In a real in-door environment, error-free transmission with a data-rate of 3.6 Gbit/s has been observed over 15 meters.

A Low Phase Noise Dual-Loop Dual-Output Frequency Synthesizer in SiGe BiCMOS

“…The millimeter-wave frequency band with rich spectrum resources is well-matched for massive data-driven communications, such as 5G, wireless high-definition video streaming, and future ultra-high-speed wireless communication. Millimeter-wave systems, in 28/39 GHz band for 5G new radio standard and in 60 GHz bands for IEEE802.11ad/WiGig standard, have been developed for the increasing data-rate demands [1][2][3][4][5][6].…”

“…are needed in the system. To simplify the synthesizer design, sliding-IF transceiver topology is often used [2,5,6], where the LO1 frequency is harmonic-related to the LO2, so one single-loop frequency synthesizer can support the transceiver application, as shown in Figure 2a. However, in sliding-IF topology, both LO1 and LO2 are variable for selecting different channels, which add complexity in wide-band IF transceiver and filter design.…”