An Integrated Digital Architecture for the Real-time Reconstruction in a VSiP Sensor

Kolar, A.; Graba, Tarik; Pinna, Andréa; Romain, Olivier; Granado, Bertrand; Thomas, Elizabeth

doi:10.1109/icecs.2006.379740

Cited by 4 publications

(4 citation statements)

References 7 publications

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“…This approach, compared to 3 or 4-pixel colour imaging, presents several improvements in spatial frequency, resolution and colour accuracy. In [106-108], De Graaf et al . proposed a microsystem for illumination source identification.…”

Section: Examples Of Applications In Integrated Cmos Optical Sensorsmentioning

confidence: 99%

A Review of the CMOS Buried Double Junction (BDJ) Photodetector and its Applications

Feruglio

Garda

et al. 2008

Sensors

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A CMOS Buried Double Junction PN (BDJ) photodetector consists of two vertically-stacked photodiodes. It can be operated as a photodiode with improved performance and wavelength-sensitive response. This paper presents a review of this device and its applications. The CMOS implementation and operating principle are firstly described. This includes the description of several key aspects directly related to the device performances, such as surface reflection, photon absorption and electron-hole pair generation, photocurrent and dark current generation, etc. SPICE modelling of the detector is then presented. Next, design and process considerations are proposed in order to improve the BDJ performance. Finally, several BDJ-detector-based image sensors provide a survey of their applications.

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Section: Examples Of Applications In Integrated Cmos Optical Sensorsmentioning

confidence: 99%

A Review of the CMOS Buried Double Junction (BDJ) Photodetector and its Applications

Feruglio

Garda

et al. 2008

Sensors

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“…Several attempts to accelerate 3D reconstruction applications utilize dedicated platforms, most notably FPGA devices for the implementation of the digital architecture [11] while other researchers use clustering for boosting performance [12]. However, all these implementations target typical two-view stereoscopic systems and there is no implementation for accelerating a full 3D surface model reconstruction method.…”

Section: Introductionmentioning

confidence: 99%

A real-time FPGA architecture for 3D reconstruction from integral images

Chaikalis

Sgouros

Maroulis

2010

Journal of Visual Communication and Image Representation

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“…The acceleration of 3D reconstruction applications has been addressed by utilizing dedicated platforms like FPGA devices [12] or by turning to clustering for boosting performance [13]. Nonetheless, they all target typical stereoscopic systems, and no attempt has been presented to accelerate a full 3D surface model reconstruction method.…”

Section: Introductionmentioning

confidence: 99%

Hardware Acceleration for 3D Image Reconstruction

Chaikalis

Passalis

Sgouros

et al. 2008

2008 Panhellenic Conference on Informatics

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This work presents a hardware acceleration scheme for a 3D reconstruction method, targeting demanding dynamic Integral Imaging applications. The architecture exploits parallel processing and minimizes memory operations by implementing an efficient metric and an extended-access memory scheme. The employed data reutilization technique reduces overall throughput allowing the use of a single FPGA. Results reveal that the hardware system accelerates the software method by an order of magnitude and its processing rate surpasses the typical rate of a dynamic Integral Imaging acquisition system, making it suitable for robust 3D image and video reconstruction applications.

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An Integrated Digital Architecture for the Real-time Reconstruction in a VSiP Sensor

Cited by 4 publications

References 7 publications

A Review of the CMOS Buried Double Junction (BDJ) Photodetector and its Applications

A Review of the CMOS Buried Double Junction (BDJ) Photodetector and its Applications

A real-time FPGA architecture for 3D reconstruction from integral images

Hardware Acceleration for 3D Image Reconstruction

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