2021
DOI: 10.1109/access.2021.3132188
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An Integrated Digital System Design Framework With On-Chip Functional Verification and Performance Evaluation

Abstract: This paper introduces a design and on-chip verification framework for IPCores in FPGA platforms. The methodology of the proposed framework is based on the development of a high level software model, an HDL description of the IPCore and the verification of the system under test by the Autotest Core, an onchip verification core developed for this framework. The test pattern generation is done at the high level in software and used throughout the design and verification process. HDL simulation results can then be… Show more

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Cited by 2 publications
(3 citation statements)
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“…When the clock counter counts to 235959, the counting state is 000000 when the next clock rising edge arrives. So basically we can assume that the counter is working fine [8].…”
Section: Confirmmentioning
confidence: 99%
See 1 more Smart Citation
“…When the clock counter counts to 235959, the counting state is 000000 when the next clock rising edge arrives. So basically we can assume that the counter is working fine [8].…”
Section: Confirmmentioning
confidence: 99%
“…When the clock counter counts to 235959, the counting state is 000000 when the next clock rising edge arrives. So basically we can assume that the counter is working fine[8].All outputs of the system in the normal working state of the clock mode are shown in Figure5.…”
mentioning
confidence: 99%
“…Los avances en sistemas complejos que involucran circuitos integrados han transformado distintos ámbitos de la vida diaria: electrónica de consumo, equipos médicos, comunicaciones, etc., a la vez que prometen seguir involucrándose en campos en evolución como el Internet de las cosas (IoT) [1]. Estos desarrollos involucran temáticas relacionadas con electrónica digital, por lo cual las instituciones de educación superior han creado asignaturas orientadas a su enseñanza.…”
Section: Introduccionunclassified