An integrated frequency synthesizer in 130 nm SiGe BiCMOS technology for 28/38 GHz 5G wireless networks

Peters, Frank; Kucharski, Maciej; Ergintav, Arzu; Borngräber, J.; Ng, Herman Jalli; Domke, Jorg; Kissinger, Dietmar

doi:10.23919/eumic.2017.8230703

Cited by 13 publications

(8 citation statements)

References 14 publications

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“…furthermore, authors (Kuo et al, 2017), proposed other model of PLL for 28 GHz band which consists of a dual loop offset PLO to improve in-band phase noise for 5G systems. In addition to the proposed works for 28 GHz band, other investigation reported by (Herzel et al, 2017) presented a design of frequency synthesizer for both 28/38 GHz frequency bands. The proposed model achieved a low Phase Noise by combining capacitive tuning and inductor switching in the voltage-controlled oscillator (VCO).…”

Section: A Pll Frequency Synthesizermentioning

confidence: 99%

High tolerance of charge pump leakage current in Integer-N PLL frequency synthesizer for 5G networks

Berber

Kameche

Benkhelifa

2019

Simulation Modelling Practice and Theory

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One of the most promising solutions for the future fifth generation communication systems is to utilize millimeter wave (mm-W) radio frequencies. There is, however, little works about Phase Locked Loop (PLL) frequency synthesizer designed for mm-W band frequency for 5G applications. This article discusses integer PLL architecture for frequency synthesis; it targets the highest range of 5G mmW [81-86] GHz using ultra-wide channel spacing of 1GHz. This work investigates the design of a third passive loop filter for frequency synthesizer using a Phase Frequency Detector and a current switch Charge Pump such as analog devices ADF4155. The critical performance for the Charge Pump depends on the leakage current produced by the technology of its transistors. This undesirable current can have a high impact on the loop stability. However, by optimizing PLL filter parameters, the synthesizer was able to tolerate up to 117 nA. With such a high leakage current, a high performance of the system was achieved. As a result, less than −71 dBc reference spur level at 50 MHz offset frequency was ensured and 3.23 µs settling time for a hopping frequency of 5 GHz was achieved.

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Section: A Pll Frequency Synthesizermentioning

confidence: 99%

High tolerance of charge pump leakage current in Integer-N PLL frequency synthesizer for 5G networks

Berber

Kameche

Benkhelifa

2019

Simulation Modelling Practice and Theory

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“…There are three kinds of PLL architectures 3 : PLL using a fundamental voltage-controlled oscillator (VCO), PLL using an N-push VCO, and PLL followed by a frequency multiplier. For the first one, [4][5][6][7] its frequency range depends on the tuning range of the VCO. In Ref.…”

Section: Introductionmentioning

confidence: 99%

X‐ and Ku‐ bands wideband low‐noise phase‐locked loop in 0.13 μm SiGe BiCMOS technology

Cheng

Wei

2022

Int J RF Mic Comp-Aid Eng

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This paper presents a 9.4 ~ 20.6 GHz low‐noise phase‐locked loop (PLL) in 0.13‐μm SiGe BiCMOS technology for 5G applications. To achieve the wideband and phase noise performance simultaneously, a four‐core Colpitts voltage‐controlled oscillato array with 2‐bit switched capacitors and 2‐bit‐control bias currents is used in the PLL loop. In order to optimize the programmable frequency divider accurately, the injection‐locking behavior model of the dual‐mode prescaler is quantitatively analyzed, which is proved to be effective through the tape‐out. The fabricated proposed PLL achieves the average phase noise of −100.5 dBc/Hz at 1‐MHz offset, wideband locking range of 74.7% and the high FOMT of 183.3 dBc/Hz. It occupies an area of 8.4 mm2, and its maximum power consumption is 319.7 mW.

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“…IVIDE-by-eight frequency dividers (FDs) are used in sliding-IF receivers [1], [2] and phase-locked loops as shown in Fig. 1 [3], [4].…”

Section: Introductionmentioning

confidence: 99%

Current Reused 8:1 Injection Locked Frequency Divider Using Unbalanced Ring Oscillator Frequency Divider

Jang¹,

Hsieh²,

Yang³

et al. 2021

IEEE Access

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This paper proposes and analyzes a CMOS divide-by-8 injection locked frequency divider (ILFD) with a divide-by-2 ring oscillator stacked on a capacitive cross-coupled oscillator used as an LC divide-by-4 ILFD. The divide-by-8 ILFD in the TSMC 0.18 μm 1P6M CMOS process has a locking range from 15.5 GHz to 17.8 GHz at the power consumption of 10 mW. The varactorless divide-by-8 ILFD occupies a small area of 0.8044×0.72 mm 2 . The ILFD can be used in divide-by-4 mode and has a locking range from 4.8 GHz to 10.6 GHz at the power consumption of 10.43 mW. The ring oscillator based frequency divider (FD) is designed with a pair of differential outputs so that the whole divide-by-8 ILFD provides differential output. The ring oscillator FD uses unbalanced component parameters to optimize the circuit performance and it supplies two unbalanced tail currents to the LC ILFD, which also provide unbalanced outputs despite the circuit topology is a symmetric one. The unbalanced approach offers design flexibility.

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An integrated frequency synthesizer in 130 nm SiGe BiCMOS technology for 28/38 GHz 5G wireless networks

Cited by 13 publications

References 14 publications

High tolerance of charge pump leakage current in Integer-N PLL frequency synthesizer for 5G networks

High tolerance of charge pump leakage current in Integer-N PLL frequency synthesizer for 5G networks

X‐ and Ku‐ bands wideband low‐noise phase‐locked loop in 0.13 μm SiGe BiCMOS technology

Current Reused 8:1 Injection Locked Frequency Divider Using Unbalanced Ring Oscillator Frequency Divider

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