An integrated linear RF power detector

Kulhalli, Suhas; Seth, Sumantra; Fu, S.-T.

doi:10.1109/iscas.2004.1328272

Cited by 15 publications

(5 citation statements)

References 5 publications

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“…If the dc offset is high, it can saturate the output which will lead to an incorrect value at the output. To compensate this, different techniques can be used such as chopper modulation [1], ac coupling [5], [8] dc subtraction [1], [2] and the use of a comparator-DAC circuit for dc offset calibration.…”

Section: Logarithmic Amplifiermentioning

confidence: 99%

Design of a Linear-in-dB Power Detector in 65nm CMOS Technology

Kiela

Jurgo

Navickas

2013

ElAEE

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In this work, design and simulation results of a linear-in-dB power detector are presented. The power detector can be used in integrated wireless communication devices for received or transmitted intermediate frequency (IF) signal power monitoring and control, local oscillator (LO) leakage detection. The whole detector block is composed of a mixer, amplifier and IF logarithmic amplifier to achieve linear-in-dB power detection. Design and simulation verification was performed using Cadence software package. The proposed integrated circuit in 65 nm CMOS technology achieves a 74 dB dynamic range, while consuming 24 mW from 1,2 V power supply.

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Section: Logarithmic Amplifiermentioning

confidence: 99%

Design of a Linear-in-dB Power Detector in 65nm CMOS Technology

Kiela

Jurgo

Navickas

2013

ElAEE

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“…In order to serve as a general-purpose BIST module, it is required that the amplitude detector exhibits valid transfer characteristics over a wide frequency band with sufficient dynamic range. According to the performance requirements, one of the most widely used techniques for amplitude detection is to utilize the exponential -characteristics of a bipolar transistor [8], [9]. For circuit implementations in a CMOS process, similar device properties can be realized by biasing the transistors in the subthreshold region [2], [7] and the schematic of the amplitude detector is shown in Fig.…”

Section: A Amplitude Detectorsmentioning

confidence: 99%

A Build-in Self-Test Technique for RF Low-Noise Amplifiers

Huang

Hsieh

2008

IEEE Trans. Microwave Theory Techn.

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A built-in self-test (BIST) technique suitable for RF low-noise amplifiers (LNAs) is presented in this paper. With fully integrated amplitude detectors and logarithmic amplifiers, the BIST module can be employed as a generic platform for gain extraction of the device-under-test (DUT) without expensive testing instruments, while maintaining a reasonable hardware overhead and minimum loading effects to the DUT. Using a 0.18-m CMOS process, a 5-GHz variable-gain LNA with the proposed BIST module is implemented. Based on the experimental results, on-chip gain extraction of the LNA has been demonstrated with an error less than 1 dB for various gain modes. The additional chip area required for the BIST functionality measures 0.042 mm 2 , which is considerably small compared with the physical size of the RF amplifiers.

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“…Reducing RF test complexity and cost is still an open research topic that has been addressed in a number of different approaches. Recent work in this area includes defect modeling and failure diagnosis [1][2][3][4], alternate test [4,5], DfT and BIST techniques [6][7][8][9][10][11][12][13][14], etc.…”

Section: Introductionmentioning

confidence: 99%

“…The use of test sensors embedded into the RF system has also been proposed [6][7][8][10][11][12][13][14]. Several built-in test schemes have been reported that use integrated peak, root-meansquare (RMS), power detectors and temperature sensors for testing discrete RF modules or complete transceivers.…”

Section: Introductionmentioning

confidence: 99%

Alternate Test of LNAs Through Ensemble Learning of On-Chip Digital Envelope Signatures

et al. 2011

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This paper presents a novel and low-cost methodology for testing embedded Low Noise Amplifiers (LNAs). It is based on the detection and analysis of the response envelope of the Device Under Test (DUT) to a two-tone input signal. The envelope signal is processed to obtain a digital signature sensitive to key specifications of the DUT. An optimized regression model based on ensemble learning is used to relate the digital signatures to the target specifications. The proposed test procedure is studied from an analytical point of view, and a demonstrator has been developed to prove the feasibility of the approach. This demonstrator features a 2.445GHz low-power LNA and a simple envelope detector, and has been

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An integrated linear RF power detector

Cited by 15 publications

References 5 publications

Design of a Linear-in-dB Power Detector in 65nm CMOS Technology

Design of a Linear-in-dB Power Detector in 65nm CMOS Technology

A Build-in Self-Test Technique for RF Low-Noise Amplifiers

Alternate Test of LNAs Through Ensemble Learning of On-Chip Digital Envelope Signatures

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