An Integrated Open Framework for Heterogeneous MPSoC Design Space Exploration

Angiolini, Federico; Ceng, Jianjiang; Leupers, Rainer; Ferrari, F.; Ferri, Cesare; Benini, Luca

doi:10.1109/date.2006.244000

Cited by 30 publications

(12 citation statements)

References 9 publications

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“…Design-time DSE strategies that generate multiple mappings for the application have recently been reported in [Mariani et al 2010;Stuijk et al 2010;Giovanni et al 2010;Zamora et al 2007;Angiolini et al 2006;Lukasiewycz et al 2008]. The generated mappings can be used to handle dynamism in resource availability and throughput requirement at runtime, but these approaches have several drawbacks, such as being applicable only to fixed platform, not providing optimal mappings in some cases, evaluating large numbers of mappings for relatively larger platforms (including some duplicate mappings), and not scaling well with the platform size.…”

Section: Related Workmentioning

confidence: 98%

Accelerating throughput-aware runtime mapping for heterogeneous MPSoCs

Singh

Kumar

Srikanthan

2013

ACM Trans. Des. Autom. Electron. Syst.

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Modern embedded systems need to support multiple time-constrained multimedia applications that often employ multiprocessor-systems-on-chip (MPSoCs). Such systems need to be optimized for resource usage and energy consumption. It is well understood that a design-time approach cannot provide timing guarantees for all the applications due to its inability to cater for dynamism in applications. However, a runtime approach consumes large computation requirements at runtime and hence may not lend well to constrained-aware mapping.In this article, we present a hybrid approach for efficient mapping of applications in such systems. For each application to be supported in the system, the approach performs extensive design-space exploration (DSE) at design time to derive multiple design points representing throughput and energy consumption at different resource combinations. One of these points is selected at runtime efficiently, depending upon the desired throughput while optimizing for energy consumption and resource usage. While most of the existing DSE strategies consider a fixed multiprocessor platform architecture, our DSE considers a generic architecture, making DSE results applicable to any target platform. All the compute-intensive analysis is performed during DSE, which leaves for minimum computation at runtime. The approach is capable of handling dynamism in applications by considering their runtime aspects and providing timing guarantees.The presented approach is used to carry out a DSE case study for models of real-life multimedia applications: H.263 decoder, H.263 encoder, MPEG-4 decoder, JPEG decoder, sample rate converter, and MP3 decoder. At runtime, the design points are used to map the applications on a heterogeneous MPSoC. Experimental results reveal that the proposed approach provides faster DSE, better design points, and efficient runtime mapping when compared to other approaches. In particular, we show that DSE is faster by 83% and runtime mapping is accelerated by 93% for some cases. Further, we study the scalability of the approach by considering applications with large numbers of tasks.

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Section: Related Workmentioning

confidence: 98%

Accelerating throughput-aware runtime mapping for heterogeneous MPSoCs

Singh

Kumar

Srikanthan

2013

ACM Trans. Des. Autom. Electron. Syst.

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“…We developed our architecture on top of the MPARM simulation framework [3,11]. MPARM is a cycle-accurate, multi-processor simulator written in SystemC that provides flexibility in terms of design space exploration.…”

Section: Mpsoc Synchronization Supportmentioning

confidence: 99%

Energy efficient synchronization techniques for embedded architectures

Ferri

Viescas

Moreshet

et al. 2008

Proceedings of the 18th ACM Great Lakes Symposium on VLSI

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We evaluate the energy-efficiency and performance of a number of synchronization mechanisms adapted for embedded devices. We focus on simple hardware accelerators for common software synchronization patterns. We compare the energy efficiency of a range of shared memory benchmarks using both spin-locks and a simple hardware transactional memory. In most cases, transactional memory provides both significantly reduced energy consumption and increased throughput. We also consider applications that employ concurrency patterns based on semaphores, such as pipelines and barriers. We propose and evaluate a novel energy-efficient hardware semaphore construction in which cores spin on local scratchpad memory, reducing the load on the shared bus.

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“…To weigh these results against, we show the relative error between DRESC and NESSIE regarding the ED 22 . In this figure, we see that: • for the variant u4-2X2mesh, we have a big error (80%) due to the significative overhead introduced by the model2 for this architecture (see section4.6.2).…”

Section: Preselection Of Solutionsmentioning

confidence: 99%

“…Therefore, it uses typically IP's provided in the industry. The paper [22] proposes to extend the capabilities of such an environment with the use of the LISAT ek tool that generates ASIP in C/C++ or in VHDL.…”

Section: Mparm(2004)mentioning

confidence: 99%