An interline CCD image sensor with reduced image lag

Teranishi, Nobukazu; Kohno, A.; Ishihara, Yasuo; Oda, E.; Arai, K.

doi:10.1109/t-ed.1984.21796

Cited by 24 publications

(8 citation statements)

References 4 publications

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“…Amongst these, we focus on the two following: the three-transistor-active-pixel (3T pixel) based on a classical P-N junction and the four-transistor-active-pixel with in pixel charge transfer (4TPPD pixel 9 ) based on a fully depleted pinned photodiode. 10 Due to their capacity to perform in-pixel double correlated double sampling (CDS), their high charge to voltage conversion factor and their extremely low dark current, 4TPPD pixels are widely used in small pitch commercial sensors. 3T pixels are still of interest for scientific applications, especially for large pitch sensors and for photon shot noise limited applications (in which the in-pixel CDS is not necessary).…”

Section: Specificities Of Image Sensors Manufactured Using Dsm Cmos Tmentioning

confidence: 99%

Radiation damages in CMOS image sensors: testing and hardening challenges brought by deep sub-micrometer CIS processes

et al. 2010

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This paper presents a summary of the main results we observed after several years of study on irradiated custom imagers manufactured using 0.18 μm CMOS processes dedicated to imaging. These results are compared to irradiated commercial sensor test results provided by the Jet Propulsion Laboratory to enlighten the differences between standard and pinned photodiode behaviors. Several types of energetic particles have been used (gamma rays, X-rays, protons and neutrons) to irradiate the studied devices. Both total ionizing dose (TID) and displacement damage effects are reported. The most sensitive parameter is still the dark current but some quantum efficiency and MOSFET characteristics changes were also observed at higher dose than those of interest for space applications. In all these degradations, the trench isolations play an important role. The consequences on radiation testing for space applications and radiation-hardening-by-design techniques are also discussed.

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Section: Specificities Of Image Sensors Manufactured Using Dsm Cmos Tmentioning

confidence: 99%

Radiation damages in CMOS image sensors: testing and hardening challenges brought by deep sub-micrometer CIS processes

et al. 2010

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“…Although more efficient with respect to space utilization, the resulting even/odd non-uniformity causes an undesirable half Nyquist moire interference pattern. Vertical antiblooming pixels are fabricated in a p-well on an n-type substrate [3,4] instead of the typical structure of in a p-epi on a p + substrate. During operation of the device without signal charge, the n-buried layer and the p-well underneath the photogate are fully depleted.…”

Section: Lateral Antibloomingmentioning

confidence: 99%

<title>Surface channel clocked antiblooming technique for area-array CCD image sensors</title>

et al. 1992

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Implementation ofover-illumination protection on area array image sensors has typically involved significant modifications to device design and/or processing. These modifications have caused degradation of device performance, for example, lateral antiblooming reduces fill factor and vertical antiblooming reduces near infra-red (NIR) quantum efficiency (QE).Clocked antiblooming is a technique that does not require any processing or design changes and does not degrade fill factor or MR QE. The technique involves clocking the imaging phases into, and out of, inversion during the integration time and relying on the surface recombination of electrons and holes to eliminate excess signal charge.The technique described in this paper allows clocked antiblooming with surface channel operation thus permitting large full well packets with small pixel geometries. Although surface channel operation is less efficient in terms of charge transfer efficiency, there are some applications where maximum full well charge storage capability is important.

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“…Optimal correlated double sampling can be implemented for suppression of kTC noise, and together with the very low sense node capacitance makes it possible to routinely achieve sub-electron read noise [ 2 ]. In addition, the dark current in PPD pixels is very low because of the nearly complete suppression of the surface electron-hole generation by the shallow pinning layer [ 3 ], which also helps to significantly reduce the image lag [ 4 ].…”

Section: Introductionmentioning

confidence: 99%

Design and Performance of a Pinned Photodiode CMOS Image Sensor Using Reverse Substrate Bias

Stefanov

Clarke

Ivory

et al. 2018

Sensors

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A new pinned photodiode (PPD) CMOS image sensor with reverse biased p-type substrate has been developed and characterized. The sensor uses traditional PPDs with one additional deep implantation step to suppress the parasitic reverse currents, and can be fully depleted. The first prototypes have been manufactured on an 18 µm thick, 1000 Ω·cm epitaxial silicon wafers using 180 nm PPD image sensor process. Both front-side illuminated (FSI) and back-side illuminated (BSI) devices were manufactured in collaboration with Teledyne e2v. The characterization results from a number of arrays of 10 µm and 5.4 µm PPD pixels, with different shape, the size and the depth of the new implant are in good agreement with device simulations. The new pixels could be reverse-biased without parasitic leakage currents well beyond full depletion, and demonstrate nearly identical optical response to the reference non-modified pixels. The observed excessive charge sharing in some pixel variants is shown to not be a limiting factor in operation. This development promises to realize monolithic PPD CIS with large depleted thickness and correspondingly high quantum efficiency at near-infrared and soft X-ray wavelengths.

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An interline CCD image sensor with reduced image lag

Cited by 24 publications

References 4 publications

Radiation damages in CMOS image sensors: testing and hardening challenges brought by deep sub-micrometer CIS processes

Radiation damages in CMOS image sensors: testing and hardening challenges brought by deep sub-micrometer CIS processes

<title>Surface channel clocked antiblooming technique for area-array CCD image sensors</title>

Design and Performance of a Pinned Photodiode CMOS Image Sensor Using Reverse Substrate Bias

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