An intra-cell defect grading tool

Abstract

With the continuous scaling down of the transistor size, the so-called intra-cell defects are more and more frequent. In this paper we propose a defect grading tool able to evaluate the efficiency of the applied test set. The test set efficiency is quantified w.r.t. the intra-cell defect coverage and the intra-cell diagnosis resolution.

Scan-Chain Intra-Cell Aware Testing

“…Several papers described this process [3][4][5]. In this work we exploit the approach published in [5]. In this section, we recall the main concepts of [5] for the sake of readability.…”

“…In our work the location can be any cell internal net. As already described in previous work [5], cell layout analysis can be used to identify the realistic defect locations. Then, for each realistic defect location, defect injection is performed to evaluate if the behavior induced by the injected defect is covered or not by the applied set of stimuli.…”

“…In [2] a statistic carried out over 1 million tested devices showed that a significant number of defects appear inside standard cells (i.e., intra-cell defects). In [3][3] [5], it is shown that these defects cannot be detected by using approaches based on classical fault models (i.e., stuck-at, transition, bridging). Despite the fact that previous works already proved that classical test sets lead to a low coverage of intra-cell defects, none of them deeply investigated the issues related to scan chain testing in the presence of intra-cell defects.…”