An investigation of drain pulse induced hot carrier degradation in n-type low temperature polycrystalline silicon thin film transistors

Zhang, Meng; Wang, Mingxiang

doi:10.1016/j.microrel.2010.01.024

Cited by 12 publications

(4 citation statements)

References 11 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Thus no HCs is generated in the t f transient, agreeing with the observed t f independent degradation. A transient simulation using continuous defect model also proves the validity of the model [11][12]. The proposed degradation model is verified by the observed degradation under fixed V d stress pulses of 0~15V with different dc V g biases from +15V to −15V.…”

Section: Introductionsupporting

confidence: 56%

“…Clearly it is observed that no degradation occurs under the dc stress condition of the same stress amplitude, while device degradation increases with pulse f. In the figure inset, degradation curves at different fs are plotted against pulse number N. All curves actually follow the same trend against N, clearly indicating that the observed degradation is associated with the pulse transition edges. Pulse rising time t r is found to be the key factor for device degradation, and shorter t r brings larger degradation, while pulse falling time t f has little impact on the degradation [11][12].…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Dynamic degradation mechanisms of low temperature polycrystalline silicon thin-film transistors

Wang

Zhang

et al. 2012

2012 19th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits

Self Cite

View full text Add to dashboard Cite

Degradation mechanisms of low temperature polycrystalline silicon (LTPS) thin-film transistors (TFTs) under various dynamic stresses are reviewed. Dynamic hot carrier (HC) mechanism under gate and drain stress pulses is interpreted based on non-equilibrium PN junction model. For synchronized gate and drain stress pulse, both dynamic HC and self-heating (SH) mechanism are involved. For n-type TFTs, device degradation is dominated by SH at low-frequencies whereas by dynamic HC at high frequencies. Besides, for p-type TFTs, negative bias temperature instability and the dynamic HC mechanisms are both effective for the degradation.Keywords: low temperature polycrystalline silicon (LTPS), thin-film transistor (TFT), dynamic stress, non-equilibrium PN junction I. INTRODUCTION Low temperature polycrystalline silicon (LTPS) thin film transistors (TFTs) are promising candidates for realizing active-matrix display system on a panel for either LCD or OLED [1]. TFTs' device reliability is always a concern for such applications, on which previous investigations covered both direct current (dc) and alternative current (ac) stress conditions [2][3][4][5][6][7][8][9]. With no doubt, ac stress conditions are more realistic considering the actual operation conditions of TFT circuits. For MOSFETs, previous studies generally agree that the ac lifetime can be estimated based on the dc lifetime corrected by a factor larger than 1 [10]. It means that DC mechanism dominates the degradation of MOSFETs. For LTPS TFTs, although they are also field effect devices similar to MOSFETs, it will be shown that various dynamic degradation mechanisms are involved and dominate the degradation under ac stress conditions [4][5][6][7][8][9].In this paper, device degradation of LTPS TFTs under dynamic drain pluses (V d ), gate pluses (V g ), and synchronized V g /V d pulses are reviewed. The stress pulses could be positive, negative and bipolar according to the pulse base voltage (V g_b ) and its amplitude (V g_a ), as shown in Fig. 1. The degradation can be understood mainly based on a non-equilibrium PN junction degradation model, which assumes that hot carriers (HCs) will be generated in the depletion region of the non-equilibrium source/drain (S/D) junction during the voltage switching of V g , V d or both.

show abstract

Section: Introductionsupporting

confidence: 56%

Section: Introductionmentioning

confidence: 99%

Dynamic degradation mechanisms of low temperature polycrystalline silicon thin-film transistors

Wang

Zhang

et al. 2012

2012 19th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits

Self Cite

View full text Add to dashboard Cite

show abstract

“…Based on these results where the device performance under AC stress showed a significant difference from DC stress tests and demonstrated a great dependence on the pulse parameters, HCEs in the channel can be regarded as having a critical influence on AC stress instability. 22,23,25 As shown in Fig. 2a, the reliability of a-IGZO TFTs is insufficient for the realization of outstanding device performance with a high switching speed.…”

Section: Resultsmentioning

confidence: 99%

“…Although hot carrier-induced degradation in low temperature polycrystalline silicon (LTPS) TFTs has been extensively investigated, the effect of hot carrier stress on the electrical properties of AOSs has not been fully clarified. 20,22–24 In poly-Si TFTs, the use of a dual-gate (DG) structure and lightly doped drain (LDD) is a representative method to mitigate the electric field near the drain side, inhibiting the hot carrier effects (HCEs). 25–27 Due to the fixed material composition of poly-Si, the method of adjusting the device structure was mainly effective for securing stability against hot carriers.…”

Section: Introductionmentioning

confidence: 99%

Solution-processed amorphous zinc indium tin oxide thin-film transistors with high stability under AC stress

Ho,

Jeong,

Park

et al. 2023

J. Mater. Chem. C

View full text Add to dashboard Cite

show abstract

Characterization of hot carrier degradation in n-type poly-Si TFTs under dynamic drain pulse Stress with DC gate bias

Zhang

Wang

et al. 2010

2010 17th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits

View full text Add to dashboard Cite

An investigation of drain pulse induced hot carrier degradation in n-type low temperature polycrystalline silicon thin film transistors

Cited by 12 publications

References 11 publications

Dynamic degradation mechanisms of low temperature polycrystalline silicon thin-film transistors

Dynamic degradation mechanisms of low temperature polycrystalline silicon thin-film transistors

Solution-processed amorphous zinc indium tin oxide thin-film transistors with high stability under AC stress

Characterization of hot carrier degradation in n-type poly-Si TFTs under dynamic drain pulse Stress with DC gate bias

Contact Info

Product

Resources

About