An Investigation of Phase Noise of a Fractional-N PLL in the Course of FMCW Chirp Generation

Ergintav, Arzu; Peters, Frank; Kissinger, Dietmar; Ng, Herman Jalli

doi:10.1109/iscas.2018.8351072

Cited by 8 publications

(4 citation statements)

References 10 publications

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“…4, this may push the beat frequencies into a region of lower phase noise. It should be noted, however, that the close-in phase noise of an analog charge-pump PLL may increase significantly if fast chirps are generated [17]. This is because fast chirps result in a large static phase error at the phase detector and thus a large charge pump duty cycle.…”

Section: Synthesizer Phase Noisementioning

confidence: 99%

“…where C is the loop filter capacitance, I CP is the charge pump current, K V is the VCO gain and T S is the sweep time. It can be shown that there is an optimum charge pump duty cycle that minimizes the close-in phase noise [17]. Therefore, the PLL parameters (i.e.…”

Section: Synthesizer Phase Noisementioning

confidence: 99%

“…C and I CP ) should be adjusted for faster chirps. Accordingly, [17] suggests having a programmable loop filter capacitance to enable phase noise optimization for a given charge pump current and chirp slope. We can generate faster chirps by reducing the chirp modulation period.…”

Section: Synthesizer Phase Noisementioning

confidence: 99%

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Design Considerations for Integrated Radar Chirp Synthesizers

et al. 2019

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Phase-locked loops (PLLs) effectively generate frequency chirps for frequency-modulated continuous-wave (FMCW) radar and are ideal for integrated circuit implementations. This paper discusses the design requirements for integrated PLLs used as chirp synthesizers for FMCW radar and focuses on an analysis of the radar performance based on the PLL configuration. The fundamental principles of the FMCW radar are reviewed, and the importance of low synthesizer phase noise for reliable target detection is quantified. This paper provides guidance for the design of chirp synthesizer PLLs by analyzing the impact of the PLL configuration on the accuracy and reliability of the radar. The presented analysis approach allows for a straightforward study of the radar performance and quantifies the optimal settings of a PLL-based chirp synthesizer for a given application scenario, while the developed methodology can be easily applied to other scenarios. A novel digital chirp synthesizer PLL design that meets the requirements of FMCW radar is presented. The synthesizer prototype fabricated in 65-nm CMOS drives a radar testbed to verify the effectiveness of the synthesizer design in a complete FMCW radar system. INDEX TERMS Chirp linearity, chirp synthesis, frequency-modulated continuous-wave (FMCW) radar, fully-integrated chirp synthesizer, phase locked loop (PLL), phase noise, PLL bandwidth, radar testbed.

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Section: Synthesizer Phase Noisementioning

confidence: 99%

Section: Synthesizer Phase Noisementioning

confidence: 99%

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Design Considerations for Integrated Radar Chirp Synthesizers

et al. 2019

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“…This was done by exploiting the fact that the feedback signal at the phase detector is available as a mono-frequency sinusoidal signal that can be measured directly with a commercial phase noise measurement device. In [11] and [12], the phase noise of the feedback signal during an FMCW chirp increases significantly compared to the mono-frequency CW operation mode. However, the measured phase noise spectra of the feedback signals at the phase detector do not correspond to the phase noise at the voltage-controlled oscillator (VCO) output.…”

Section: Introductionmentioning

confidence: 99%

Phase Noise Spectral Density Measurement of Broadband Frequency-Modulated Radar Signals

Tschapek

Korner

Hofmann

et al. 2022

IEEE Trans. Microwave Theory Techn.

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In continuous-wave (CW) radar systems, such as frequency-modulated (FMCW), frequency-stepped (FSCW), or orthogonal frequency-division multiplexing (OFDM) radar systems, the range and velocity uncertainty are significantly impaired by phase noise decorrelation. Therefore, radar designers require accurate knowledge of their synthesizers' phase noise profiles to assess and predict radar performance. However, commercial phase noise analyzers cannot determine phase noise during modulation, and this may differ notably from phase noise in the pure CW mode. Recent methods for FMCW phase noise analysis usually require comprehensive a priori knowledge of modulation parameter and are prone to systematic deviations. To overcome these issues, we propose a new approach based on differential analysis of subsequent time-domain measurements. This method retains, statistical phase noise information while reducing systematic influences. For the first time, less a priori signal knowledge is required, and the method works for nearly any kind of broadband signal modulation. The concept requires only a digitizer (e.g., an oscilloscope) and some digital signal processing. The proposed method is first experimentally tested with different phase-locked-loop (PLL)-based synthesizer phase noise profiles. The obtained phase noise profiles agree perfectly with the results of an established measurement system. After this proof of basic functionality, the unique phase noise analysis capability for BB modulated signals is demonstrated with PLL-generated FMCW signals. The results reveal a significant phase noise difference between the different setups and clearly show the capability and benefit of the novel phase noise spectral density measurement concept.

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A 15-GHz Reconfigurable Calibration-Free Linear FMCW Chirp Generator with Type-III Nested-PLL

Wang,

Fu,

et al. 2023

2023 Asia-Pacific Microwave Conference (APMC)

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An Investigation of Phase Noise of a Fractional-N PLL in the Course of FMCW Chirp Generation

Cited by 8 publications

References 10 publications

Design Considerations for Integrated Radar Chirp Synthesizers

Design Considerations for Integrated Radar Chirp Synthesizers

Phase Noise Spectral Density Measurement of Broadband Frequency-Modulated Radar Signals

A 15-GHz Reconfigurable Calibration-Free Linear FMCW Chirp Generator with Type-III Nested-PLL

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