“…A test subsequence S detects the functional delay fault fd i if the subsequence S satisfies all three mentioned at the beginning of this section conditions: 1. the circuit is brought into state, required for activation of fd i ; 2. the functional delay fault fd i is activated; 3. the effect of fd i is propagated to a primary output. According described in [6,7] approaches the test generation process proceeds in following way. The whole particular subsequence S k is generated randomly, then using fault simulation the set of functional delay faults that S k detects is defined, and if S k detects any not yet detected faults, S k is included into resulting test sequence.…”