An investigation on steep-slope and low-power nanowire FETs

Abstract

In this work we investigate by numerical simulation the achievable performance of a steep-slope nanowire FET based on the filtering of the high-energy electrons by a superlattice heterostructure in the source extension. After a preliminary study aimed to identify the most promising material pairs for the superlattice with respect to the typical FET evaluation metrics, we concentrate on a superlattice-based FET employing the InGaAsInAlAs pair, which provides a good switching slope and an excellent on-current. The device optimization leads to a prediction of an inverse SS = 35 mV/dec and an on-current exceeding 2.3 mA/µm at a supply voltage of 400 mV. I. INTRODUCTIONPower consumption has become in the last decade one of the most important limitations for high-performance logic and the main reason for its growth across several technology nodes has been the non-scalability of the FET subthreshold slope (SS). The present limit of 60 mV/dec at room temperature, however, is due to fundamental thermodynamic principles related with the energy distribution of carriers in equilibrium, and cannot be easily overcome. Besides, for bulk CMOS technologies and partially depleted SOI, the SS is often around 100 mV/dec and, in order to ensure a high switching speed, a leakage current as large as 0.1µA/µm must be tolerated for high-performance (HP) FETs [1]. The objective of a current turn-on rate much steeper than 60 mV/dec has been pursued by several approaches, some of which are mentioned in the ITRS document addressing emerging devices [1]. One of the most popular approaches is based on the idea of filtering out the high-energy electrons injected into the channel, thus effectively cooling down their energy distribution. The typical example of this approach is the tunnel FET (T-FET) [2], [3], [4], where the filtering function is entrusted to the band-to-band tunneling (BTBT) mechanism. However, BTBT injection suffers severe limitations of the on-state current, and the sustained switching slope is often disappointing. In addition, the upward curvature of the output characteristics and the related small drain conductance at zero V DS limits the T-FET performance below that of standard CMOS FETs operating at the same supply voltages [5]. In order overcome the above limitations, a new device concept was devised, where the filtering function is taken care of by a superlattice (SL) interposed between the source and the channel of a nanowire (NW) FET [6]. In this work, numerical investigations show the effectiveness of the SL to filter out the high-energy electrons and to enhance the FET switching slope.

Steep-Slope Devices: Prospects and Challenges

“…At the opposite side, the InAs-GaSb pair does not provide any serious improvement with respect to the traditional SS = 60 mV/dec [23]. It is worth noting that, in contrast with TFETs, the SL-FET shows a high output conductance at zero V DS ; hence the device is more suited for rail-to-rail logic applications.…”